Reducing analog cell layout time with the symbolic editor.

In the last blog post I profiled the use of the symbolic editor for rapid digital cell layout.

In this post we will tackle analog cell layout and show some more of the symbolic editor features that enable analog layout engineers to complete their layout in minutes versus hours.

As with the digital cell layout, the engineer can take advantage of the symbolic editor’s ability to define multiple P and N row pairs as shown in Figure 1.

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Rapid custom digital cell layout with the symbolic editor

In Custom Compiler Layout Assistants – part 1 we profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern like for example a differential pair very easy. With no constraints to enter, no code to write, layout is done in minutes versus hours.

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Custom Compiler In-Design Assistants – part 3

In the blog Custom Compiler In-Design Assistants Part 2, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS clean. In addition to capacitance reports we also showed resistance reporting which is critical for FinFET based layouts. At advanced nodes, the impact of parasitics, electro-migration (EM) and restricted design rules, drive critical layout choices. Interconnect that does not meet resistance or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase, the layout engineer can address these issues, the sooner he or she can close the design.

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Custom Compiler In-Design Assistants – part 2

Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?

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Custom Compiler In-Design Assistants – part 1

On line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every Layout engineer has a love / hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.

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Custom Compiler Layout Assistants – part 2

In the last blog I detailed the symbolic editor layout assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant the router. The routing task is one that absolutely screams out for an automated approach however past efforts have required a great deal of text-based constraints to get anything near to what you really want.

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Custom Compiler Layout Assistants – part 1

On March 30th Silicon Valley was buzzing with excitement. Synopsys held the Silicon Valley SNUG event and revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse. During the event the R&D folks did a walkthrough of the technology ‘under the hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

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What do layout engineers really need for FinFET – part 2.

In the last of blog we outlined the kind of tool that the layout engineer needs in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided / interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

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What do layout engineers really need for FinFET – part 1

Over the last series of blogs we have looked at what tools the layout engineer has available to him/her to help them deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET based layout versus a planar CMOS layout. When I asked my layout colleagues “how much longer does it take to do a FinFET based design versus planar CMOS?” they said it takes 2-3X more time.

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