Posted by Graham Etchells on December 18, 2015
I left off in part 2 of this blog asking the question “have we exhausted all avenues in our search for layout productivity?”
Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.
On line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout making it easy to find and fix them. However checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.
As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough why not show them dynamically as layout geometries were being created. And so Design Rule Driven (DRD) layout was born.
Dynamically seeing potential violations as they occur helped the layout engineer avoid creating real violations that would have to be found with an on line DRC run. This reduced the number of DRC iterations and gave a bit more productivity to the layout engineer.
With powerful workstations and real-time DRC engines things started to get even more interesting.
Remember SDL in the prior post and how with the logical connectivity visually displayed it helped in connecting up devices. Well if you could now see where you need to connect to and with DRC engines under the hood, why not simply point to the net you wanted to route and have a router do it for you. Voila, the ‘point to point’ router was born. These routers have had a few incarnations. Some simply allowed you to pick a start and endpoint and then the router completed the route using the metal layers and preferred routing directions from a technology file. Others required some intermediary points to help guide the router through specific areas of the layout. In general they are still the exception rather than the rule for a layout designer.
So with all the incremental improvements, custom layout is doing ok on the productivity front.
The bulk of todays’ design starts are at the established nodes above 28 nm, with planar CMOS being the most common process. Along the way the tools have been tweaked and tuned to enable the layout engineers to be as productive as possible as the industry sails along with the tide of shrinking process nodes.
However, be warned! The waters are about to get choppy. A hurricane has made land fall and its name is FinFET.