Custom Layout Insights: Analog/Custom Layout Blog

I know HSPICE is not strictly a layout blog subject but for those of you who do the ‘Full Monty’ of design and layout consider going along to the SPICE/AMS event and check out the HSPICE SIG event. It’s at the Santa Clara Marriott Hotel on February 2nd (next Thursday). At this event, distinguished speakers from Xilinx, ARM, Synopsys Mixed-signal IP Group, and Synopsys R&D will share their insights about using HSPICE to address some of the key challenges related to FinFET design and verification. Additionally, you will also have an opportunity to interact with Synopsys HSPICE R&D personnel as well as HSPICE Integrator Program (HIP) partners.

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There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a third of those who responded plan to use FinFET technologies on their next chip.

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In the last blog post I profiled the use of the symbolic editor for rapid digital cell layout.

In this post we will tackle analog cell layout and show some more of the symbolic editor features that enable analog layout engineers to complete their layout in minutes versus hours.

As with the digital cell layout, the engineer can take advantage of the symbolic editor’s ability to define multiple P and N row pairs as shown in Figure 1.

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In Custom Compiler Layout Assistants – part 1 we profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern like for example a differential pair very easy. With no constraints to enter, no code to write, layout is done in minutes versus hours.

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In the blog Custom Compiler In-Design Assistants Part 2, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS clean. In addition to capacitance reports we also showed resistance reporting which is critical for FinFET based layouts.  At advanced nodes, the impact of parasitics, electro-migration (EM) and restricted design rules, drive critical layout choices.  Interconnect that does not meet resistance or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase, the layout engineer can address these issues, the sooner he or she can close the design.

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DAC 2016 saw the first Custom Design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Senior VP and General Manager of the Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team.

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On line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every Layout engineer has a love / hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.

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In the last blog I detailed the symbolic editor layout assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant the router. The routing task is one that absolutely screams out for an automated approach however past efforts have required a great deal of text-based constraints to get anything near to what you really want.

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Remember the last few blogs where I was outlining the kind of tools you really need to tackle FinFET? Well they are here right now, because today Synopsys unveiled Custom Compiler and ushered in a new era of Visually-assisted Automation.

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In the last of blog we outlined the kind of tool that the layout engineer needs in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided / interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

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