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Archive for the 'Wide I/O2' Category

 

The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2 |