Committed to Memory

Archive for the 'Signal Integrity' Category


Breaking down another memory wall

People are sometimes surprised when I tell them that more than $40 Billion of DRAM chips are sold every year – but have you ever wondered where they all go?

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Posted in DDR Controller, DDR4, DIMM, IP, Signal Integrity


Do you need DDR4 Write CRC?

A customer asked us, “Do I need DDR4 write CRC beyond a certain frequency?”

The answer is far from simple; it’s dependent on many factors including the type of system it is, the other types of error correction (ECC) that may be in use, the system’s tolerance of errors, and the system’s ability to spare the bandwidth required for the write CRC function. Since I’ve been asked a few times and since the answer is so complex, I created the flowchart here to show some paths through the possible choices.

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Posted in DDR Controller, DDR4, DRAM Industry, Featured, Signal Integrity, Uncategorized


Row Hammering: What it is, and how hackers could use it to gain access to your system

I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.

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Posted in DDR3, DDR4, DIMM, DRAM Industry, Signal Integrity, Uncategorized


Synopsys DDR3 PHY Now Available for Intel’s 22nm Tri-Gate Process

It’s DAC time again and that means lots of EDA and IP related announcements.

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Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity


The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2


Synopsys Announces Complete LPDDR4 IP Solution

We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity


“How Fast Can My DDR Go?”

As a provider of DDR PHY and controller IP, the question we get asked the most goes something like this:  “Will your PHY support a {insert short description of system here} at {fill in the speed here} Mbps?  Lately, I am receiving a lot of questions around DDR4 such as “Will your DDR4 PHY support one dual rank UDIMM at 2667Mbps”?

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Posted in DDR Controller, DDR PHY, DDR4, DIMM, IP, Signal Integrity


Happy 10th Birthday DDR4!

Believe it or not, work the DDR4 standard was first started back in 2004.  That’s now 10 years ago!  Happy 10th birthday DDR4.  10 years ago Facebook was started up, there was no Twitter (2006), no iPhone (2007), and Google went public for $85/share (it is now $1,123/share).  Even after those 10 years, you can’t go out a buy a computer with DDR4 in it.  The JEDEC standard for DDR4 was published in September 2012 so why isn’t everyone using it?  Why did it take so long?

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Posted in DDR4, DRAM Industry, Low Power, LPDDR3, LPDDR4, Signal Integrity