Committed to Memory

Archive for the 'LPDDR4' Category


Apple iPhone 6S: LPDDR4 arrives at Apple

As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.

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Posted in DDR Controller, DDR PHY, LPDDR3, LPDDR4


WOW That Was Fast – JEDEC Publishes the LPDDR4 Standard

JEDEC officially published the LPDDR4 standard today.  It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication.  That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market.  The JEDEC committees responsible for this latest publication should be very proud of their achievement.  Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.

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Posted in DDR Controller, DDR PHY, LPDDR4


The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2