As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.
Posted in DDR Controller, DDR PHY, LPDDR3, LPDDR4
Our friends in Synopsys’s Verification Group have been putting together an excellent set of Memory Verification IP (VIP) for DDR4, DDR3, LPDDR4, LPDDR3, that complements our other VIP for Flash, MIPI, PCIe, AMBA, Ethernet, HDMI, SATA, etc…
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, LPDDR3, LPDDR4
I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.
A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course. One thing is certain; the future will not be an easy path for DRAMs. The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies. After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment. Unfortunately, that something else will likely be “somethings” else. Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.
Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2
We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity
Believe it or not, work the DDR4 standard was first started back in 2004. That’s now 10 years ago! Happy 10th birthday DDR4. 10 years ago Facebook was started up, there was no Twitter (2006), no iPhone (2007), and Google went public for $85/share (it is now $1,123/share). Even after those 10 years, you can’t go out a buy a computer with DDR4 in it. The JEDEC standard for DDR4 was published in September 2012 so why isn’t everyone using it? Why did it take so long?
Posted in DDR4, DRAM Industry, Low Power, LPDDR3, LPDDR4, Signal Integrity
For years, I have been predicting that Low-Power DDR (LPDDR) devices would make the crossover from mobile devices into laptops.
Posted in DDR3, DRAM Industry, Featured, Low Power, LPDDR3
Happy New Year to all our blog readers!
Posted in DRAM Industry, Low Power, LPDDR3, LPDDR4
Mobile DRAM has certainly come a long way in the last few years, but I didn’t expect to see this prediction quite so soon, that “…the shipment of mobile DRAM is likely to officially surpass that of PC DRAM in 2014”.
LPDDR3 is in the house… the Greenberg house that is!
Graham Allan
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.