Committed to Memory

Archive for the 'IP' Category

 

Breaking down another memory wall

People are sometimes surprised when I tell them that more than $40 Billion of DRAM chips are sold every year – but have you ever wondered where they all go?

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Posted in DDR Controller, DDR4, DIMM, IP, Signal Integrity |

 

Synopsys DDR3 PHY Now Available for Intel’s 22nm Tri-Gate Process

It’s DAC time again and that means lots of EDA and IP related announcements.

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Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity |

 

Synopsys’ New IP Accelerated Initiative

Synopsys made an exciting announcement today launching our new IP accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their SoCs. This initiative augments Synopsys’ broad portfolio of DesignWare® IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With the IP Accelerated initiative, Synopsys goes beyond the traditional IP supplier paradigm, redefining what customers can expect from their IP providers to help them successfully integrate IP with less effort, lower risk and faster time-to-market.

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Posted in IP |

 

The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2 |

 

Synopsys Announces Complete LPDDR4 IP Solution

We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity |

 

Qualcomm announces first application processor with LPDDR4 capability

This happened a little bit quietly last week – but Qualcomm has announced the first product that I’m aware of that will use LPDDR4 memory.

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Posted in DDR Controller, DDR PHY, IP, Low Power, LPDDR4, Uncategorized |

 

“How Fast Can My DDR Go?”

As a provider of DDR PHY and controller IP, the question we get asked the most goes something like this:  “Will your PHY support a {insert short description of system here} at {fill in the speed here} Mbps?  Lately, I am receiving a lot of questions around DDR4 such as “Will your DDR4 PHY support one dual rank UDIMM at 2667Mbps”?

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Posted in DDR Controller, DDR PHY, DDR4, DIMM, IP, Signal Integrity |

 

New DDR Memory Controller Release

I’m going to very occasionally use this blog to talk about my products, especially when I have a new product to talk about.

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Posted in DDR Controller, DDR3, DDR4, DIMM, IP, LPDDR3 |

 

Going Purple

Hello and welcome to the Synopsys DDR Blog!

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Posted in DDR Controller, IP |