It’s been about 9 months since I blogged on Samsung’s public roadmap and the fact that it carried some 3D Stacked DDR4 Devices using Through Silicon Vias (TSVs). Time for a quick update…
Posted in DDR4, DIMM, DRAM Industry, Featured, Uncategorized
I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.
Posted in DDR3, DDR4, DIMM, DRAM Industry, Signal Integrity, Uncategorized
Samsung has posted their DDR4 product guide on their website, and it gives us excellent insight into the direction that Samsung plans to go with DDR4 in the next few months with a lot of data that wasn’t previously publicly available.
Posted in DDR4, DIMM, DRAM Industry, Uncategorized
Graham Allan
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.
