Committed to Memory

Archive for the 'DDR3' Category

 

Want to learn about DDR VIP?

Our friends in Synopsys’s Verification Group have been putting together an excellent set of Memory Verification IP (VIP) for DDR4, DDR3, LPDDR4, LPDDR3, that complements our other VIP for Flash, MIPI, PCIe, AMBA, Ethernet, HDMI, SATA, etc…

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, LPDDR3, LPDDR4 |

 

Row Hammering: What it is, and how hackers could use it to gain access to your system

I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.

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Posted in DDR3, DDR4, DIMM, DRAM Industry, Signal Integrity, Uncategorized |

 

Zero to Green Light in minutes: Prototype your DDR Designs faster with new DDR IP Prototyping Kit

I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DIMM, LPDDR3 |

 

Synopsys DDR3 PHY Now Available for Intel’s 22nm Tri-Gate Process

It’s DAC time again and that means lots of EDA and IP related announcements.

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Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity |

 

The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2 |

 

Synopsys Announces Complete LPDDR4 IP Solution

We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity |

 

Two DDR Tidbits

The definition of tidbit is:

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Posted in DDR3, DDR4 |

 

The first DDR4 DIMMs are for sale!

I think I have found the first DDR4 DIMMs available for consumer purchase anywhere. Crucial and a few others were showing DDR4 DIMMs at this year’s Consumer Electronics Show (CES) in January, so it’s nice to see that they translated into real products.

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DIMM, DRAM Industry, Uncategorized |

 

When is LPDDR3 not LPDDR3? When it’s DDR3L…

For years, I have been predicting that Low-Power DDR (LPDDR) devices would make the crossover from mobile devices into laptops.

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Posted in DDR3, DRAM Industry, Featured, Low Power, LPDDR3 |

 

Crucial announces DDR4 Module Availability

Crucial memory, the DIMM division of Micron, have announced availability of DDR4 DIMM modules in early 2014.

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Posted in DDR3, DDR4, DIMM, DRAM Industry |