As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.
Posted in DDR Controller, DDR PHY, LPDDR3, LPDDR4
There was a huge technology announcement on 3D XPoint(tm) technology about 3 weeks ago – but without many details. I’m at the IDF2015 conference in San Francisco this week and we learned a lot more.
Posted in DDR Controller, DDR PHY, DDR4, DIMM, DRAM Industry, Uncategorized
Our friends in Synopsys’s Verification Group have been putting together an excellent set of Memory Verification IP (VIP) for DDR4, DDR3, LPDDR4, LPDDR3, that complements our other VIP for Flash, MIPI, PCIe, AMBA, Ethernet, HDMI, SATA, etc…
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, LPDDR3, LPDDR4
Samsung made a big event of the launch of the Galaxy S6 today (April 10th, 2015) making the S6 and S6 Edge available at multiple US and international retailers simultaneously. The Galaxy S6 is based around Samsung’s own Exynos 7420 application processor and LPDDR4 DRAM.
Posted in DDR Controller, DDR PHY, DDR4, DRAM Industry, Low Power, LPDDR4, Uncategorized
I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.
Yesterday was Memcon time again. Memcon is the event that Denali started as a one-day conference in Silicon Valley that is all about memory. After Cadence acquired Denali, Cadence now hosts the event.
Posted in DDR Controller, DDR PHY, DDR4, LPDDR4
JEDEC officially published the LPDDR4 standard today. It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication. That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market. The JEDEC committees responsible for this latest publication should be very proud of their achievement. Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.
Posted in DDR Controller, DDR PHY, LPDDR4
Following today’s event in Seoul, there are still two more JEDEC LPDDR4 Workshops and Mobile Forums coming up in the next few weeks.
Posted in DDR Controller, DDR PHY, DRAM Industry, Low Power, LPDDR4
It’s DAC time again and that means lots of EDA and IP related announcements.
Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity
We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity
Graham Allan
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.