Committed to Memory

Archive for the 'DDR Controller' Category

 

Apple iPhone 6S: LPDDR4 arrives at Apple

As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.

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Posted in DDR Controller, DDR PHY, LPDDR3, LPDDR4

 

Do you need DDR4 Write CRC?

A customer asked us, “Do I need DDR4 write CRC beyond a certain frequency?”

The answer is far from simple; it’s dependent on many factors including the type of system it is, the other types of error correction (ECC) that may be in use, the system’s tolerance of errors, and the system’s ability to spare the bandwidth required for the write CRC function. Since I’ve been asked a few times and since the answer is so complex, I created the flowchart here to show some paths through the possible choices.

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Posted in DDR Controller, DDR4, DRAM Industry, Featured, Signal Integrity, Uncategorized

 

WOW That Was Fast – JEDEC Publishes the LPDDR4 Standard

JEDEC officially published the LPDDR4 standard today.  It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication.  That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market.  The JEDEC committees responsible for this latest publication should be very proud of their achievement.  Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.

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Posted in DDR Controller, DDR PHY, LPDDR4