Committed to Memory

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Graham Allan

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Posts by Graham Allan:

 

When is “First” Really “First”?

Yesterday was Memcon time again.  Memcon is the event that Denali started as a one-day conference in Silicon Valley that is all about memory.  After Cadence acquired Denali, Cadence now hosts the event.

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Posted in DDR Controller, DDR PHY, DDR4, LPDDR4 |

 

WOW That Was Fast – JEDEC Publishes the LPDDR4 Standard

JEDEC officially published the LPDDR4 standard today.  It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication.  That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market.  The JEDEC committees responsible for this latest publication should be very proud of their achievement.  Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.

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Posted in DDR Controller, DDR PHY, LPDDR4 |

 

Synopsys DDR3 PHY Now Available for Intel’s 22nm Tri-Gate Process

It’s DAC time again and that means lots of EDA and IP related announcements.

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Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity |

 

Synopsys’ New IP Accelerated Initiative

Synopsys made an exciting announcement today launching our new IP accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their SoCs. This initiative augments Synopsys’ broad portfolio of DesignWare® IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With the IP Accelerated initiative, Synopsys goes beyond the traditional IP supplier paradigm, redefining what customers can expect from their IP providers to help them successfully integrate IP with less effort, lower risk and faster time-to-market.

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Posted in IP |

 

The Future of DRAM

A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course.  One thing is certain; the future will not be an easy path for DRAMs.  The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies.  After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment.  Unfortunately, that something else will likely be “somethings” else.  Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.

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Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2 |

 

Two DDR Tidbits

The definition of tidbit is:

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Posted in DDR3, DDR4 |

 

“How Fast Can My DDR Go?”

As a provider of DDR PHY and controller IP, the question we get asked the most goes something like this:  “Will your PHY support a {insert short description of system here} at {fill in the speed here} Mbps?  Lately, I am receiving a lot of questions around DDR4 such as “Will your DDR4 PHY support one dual rank UDIMM at 2667Mbps”?

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Posted in DDR Controller, DDR PHY, DDR4, DIMM, IP, Signal Integrity |

 

Happy 10th Birthday DDR4!

Believe it or not, work the DDR4 standard was first started back in 2004.  That’s now 10 years ago!  Happy 10th birthday DDR4.  10 years ago Facebook was started up, there was no Twitter (2006), no iPhone (2007), and Google went public for $85/share (it is now $1,123/share).  Even after those 10 years, you can’t go out a buy a computer with DDR4 in it.  The JEDEC standard for DDR4 was published in September 2012 so why isn’t everyone using it?  Why did it take so long?

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Posted in DDR4, DRAM Industry, Low Power, LPDDR3, LPDDR4, Signal Integrity |

 

The Ottawa Connection to DRAM

Hi, my name is Graham Allan and I am the Product Marketing Manager for DDR PHYs at Synopsys and a co-author of this new Blog about memory.  I happen to live in Ottawa Canada which for many of you is an odd location for anyone that has anything to do with DRAM.  I thought it may be interesting to write about the Ottawa connection to DRAM, a story that most people do not know about.

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Posted in DRAM Industry |