Posted by Marc Greenberg on August 19, 2015
There was a huge technology announcement on 3D XPoint(tm) technology about 3 weeks ago – but without many details. I’m at the IDF2015 conference in San Francisco this week and we learned a lot more.
During the big keynote presentation at IDF, 3D Xpoint(tm) was discussed for about 7 minutes, with information we had heard before – 1000x faster than NAND flash, more dense than DRAM – and then we saw a live demo of an SSD containing the 3D XPoint technology. The 3D XPoint SSD gave about 7X more IOPS than the fastest NAND SSD… They also announced that the name for products based on 3D XPoint is “Optane”. Finally, a surprise announcement, that Optane products would be available in 2016 SSD format, as well as in a DDR4 DIMM format.
The DIMM form factor is not a total industry secret… one of my contacts at an OEM said he had been discussing it with Micron for some time, but the NDAs are holding up pretty well…
Then we got more details in a packed session at the end of the day with Rob Crooke (SVP & GM of Memory Solutions Group) and Al Fazio (Senior Fellow and Director, Memory Technology Development) that discussed the 3D XPoint technology. While some of it was scripted, much of the useful information came in about 30 minutes at the end where they answered MANY questions from the floor (which are not in the slides of course). You can get the presentation of the scripted part from http://www.intel.com/idfsessionsSF and search for session SPCS006. Most of he questions from the floor were artfully crafted to find out more without asking direct questions that couldn’t be answered.
The details below assume you know a little something about this technology already. If you want to understand the basics, there’s a great infographic at http://www.intelsalestraining.com/memorytimeline/
I’m going to repeat the information as I heard it, without speculation. If you want speculation or analysis, come talk to me personally…
The session started with a quote from van Neumann in 1946 where he predicted a tiered memory system. XPoint seems to be an obvious new tier in the memory for certain applications.
– Rob and Al showed a wafer of 128Gb on 20nm process and said there is working silicon (and a working SSD was shown in the keynote). The dies on the wafer appeared to be about the maximum size for a die, probably 20-25mm from where I was sitting.
– The memory is built above the metallization layer. There is a switch element and a storage element between alternating metallization layers. Sense amps and other structures are in the silicon below.
– Because the memory is all above the metallization layer, one could theoretically could have logic (ie., a CPU) in the silicon under Xpoint. But, since the memory is using all the metal layers, no benefit in using the underlying silicon because you can’t connect it to anything.
– How many decks (or layers) are there on the die? The first generation is 2 decks. Future will be more decks. They said an economical number will be 4-8 decks.
– It shrinks lithographically, which means that Moore’s Law can continue
Use in the system:
– Earlier in the day during the keynote presentation, it was announced that there would be both SSDs and DIMMs based on the 3D XPoint technology
– 3D Xpoint SSDs will use NVMe as the interface technology. They claim the whole reason they pushed transition from SATA/SAS to NVMe because they knew the 3D Xpoint technology was coming…
– In the keynote, they showed 7X system performance by replacing a very fast NAND SSD with Xpoint. In this session they answered, ‘why only 7X’? The answer is Amdahl’s law – by increasing the speed of SSD accesses, they moved the bottleneck to somewhere else in the system. So to take full advantage of 3D XPoint technology, they need to move it to the DRAM bus, that’s why there’s DIMMs.
– The next generation Xeon (Gen 8) processor will support 3D Xpoint / Optane on the DDR bus in 2016. There will be a multi-tiered memory system on the DRAM bus, so there will be one DDR4 DIMM used as write-back cache, and one DIMM as 3D Xpoint (ie. 2 DIMMs per Channel) and will provide 4X the system memory capacity at lower cost than DRAM. They don’t anticipate that it will interfere with the performance of the DRAM.
– The technology requires optimized memory controller when on the DRAM bus in DIMM form.
– Latency is still ~10X greater than DRAM… but ~1000X better than NAND Flash (directly). In an SSD, expect ~10X latency improvement compared to NAND SSD.
Value proposition for 3D XPoint:
– Claiming ~10x larger latency than DRAM and ~10X capacity compared to DRAM (therefore, larger and theoretically less expensive than DRAM – but nobody is claiming this will be as cheap as NAND Flash)
– Claiming ~1000X write endurance improvement over NAND Flash (therefore, much slower to wear out, can be used in different applications than NAND)
– Random Access like DRAM (unlike block access of NAND)
– Non-Volatile like Flash
Theory of operation and other questions that people had:
– Unlike other memories which generally rely on stored charge, 3D XPoint relies on bulk properties of the material between the word and bit lines.
– It has some similarity to ReRAM, in that it changes resistance. But it is not filamentary – ReRAM is filamentary. This is bulk property of the material that changes.
– The XPoint technology is capable of MLC operation, but first generation is not MLC. Need to get manufacturing variability resolved before MLC comes into the picture. It took many years to go from SLC NAND to MLC NAND.
– Retention is measured in years.
– There are temperature ranges, they won’t say what, but it will be “normal limits”.
– The devices can be re-flow soldered.
– It has predictable, low latency. The write latency is deterministic. Reads are also deterministic. (Like DRAM, unlike NAND)
– Electrically and Physically compatible with DDR4, but requires a new controller.
– Both read and write are 1000X faster than NAND
– It does require wear leveling
– Ultimately the 3D XPoint technology could go into the embedded space. M.2 SSD Form Factor is good for embedded. Long term the 3D Xpoint could be provided in BGA form factor.
– No additional ECC required.
And finally, that amazingly prescient quote from the year 1946:
“ Ideally one would desire an indefinitely large memory capacity such that any particular … word would be immediately available. … It does not seem possible physically to achieve such a capacity. We are therefore forcedto recognize the possibility of constructing a hierarchy of memories, each of which has greater capacity than the preceding but which is less quickly accessible.”
Preliminary Discussion of the Logical Design of an Electronic Computing Instrument
Arthur Burks, Herman Goldstine and John von Neumann, 1946
Once again, this is the information as I heard it. I’m not perfect. There are no guarantees on the technical specifications or the dates. I am specifically not commenting on Synopsys’s plans for this technology.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.