Posted by Marc Greenberg on July 8, 2015
It’s been about 9 months since I blogged on Samsung’s public roadmap and the fact that it carried some 3D Stacked DDR4 Devices using Through Silicon Vias (TSVs). Time for a quick update…
I’ve been looking for places that I could buy one of the DIMMs – to get an idea of the cost as much as anything – for a while. I was recently able to find an online price at Amazon.com for the 64GB TSV DIMM – only $1699.00 (with free shipping!). For comparison, on the same day, a similar but half capacity 32GB Samsung DIMM based on non-stacked 8Gb DDR4 dies was $352.50 on Amazon.com . Prices may fluctuate by the time you read this of course. The short summary is that the TSV devices offer 2X the capacity at over 4X the cost (on the day I looked).
I don’t want to give anyone the impression that this price differential on TSV stacked devices will exist forever. In fact, I recently blogged that the cost/benefit on 3D Stacked HBM devices is almost balanced. The DDR4 3DS Devices are among the first of their kind and carry a premium that may be as much to do with their rarity as their cost of production.
So why would anyone consider these TSV devices? Well, there’s a few good reasons:
– Building the highest capacity servers starts with the highest capacity DIMMs. If your DIMM sockets are already ‘maxed out’ with non-stacked x4 DIMMs carrying 8Gb dies, then ‘the only way is up’.
– Providing more capacity in less unit volume compared to adding more packages or more DIMMs. This can be critical for devices like enterprise-class SSDs where PCB area and volume is at a premium.
– Potentially improved performance compared to multirank solutions. The structure of 3DS devices means that there is the potential for intra-stack operations to happen with less delay than inter-rank operations. This can improve performance in some applications (in-memory computing, for example).
– Adding capacity without adding bus loading. You may not have ‘maxed out’ the bus, but you may want to add capacity without adding additional bus load. Reducing load on the bus will tend to decrease the power substantially and increase the maximum achievable frequency in that system. A key feature of the 3DS packages is that they present a single load to the bus regardless of how many dies are in the stack.
It’s that last point that confuses a lot of people. How can you have a stack of 4 dies that only presents one load to the bus? The picture above helps to explain. Inside the DDR4 3DS package, there is typically only one physical interface (Clock, Command, Address, Data, Data strobes, etc) on a master die that is connected to the outside of the package, and all the DRAM traffic to the master die and all of the slave dies inside the package go through that one physical interface on the master die. Inter-die communication within the stack from the master to the slaves is carried on the through silicon vias (TSVs) through the stack.
So there you have it: DDR4 3DS Devices – increased DRAM capacity without increasing PCB area or bus loading, at a price.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.