As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.
Posted in DDR Controller, DDR PHY, LPDDR3, LPDDR4
It’s been about 9 months since I blogged on Samsung’s public roadmap and the fact that it carried some 3D Stacked DDR4 Devices using Through Silicon Vias (TSVs). Time for a quick update…
Posted in DDR4, DIMM, DRAM Industry, Featured, Uncategorized
A customer asked us, “Do I need DDR4 write CRC beyond a certain frequency?”
The answer is far from simple; it’s dependent on many factors including the type of system it is, the other types of error correction (ECC) that may be in use, the system’s tolerance of errors, and the system’s ability to spare the bandwidth required for the write CRC function. Since I’ve been asked a few times and since the answer is so complex, I created the flowchart here to show some paths through the possible choices.
Posted in DDR Controller, DDR4, DRAM Industry, Featured, Signal Integrity, Uncategorized
AMD announced their new line of GPUs are using the new HBM (High Bandwidth Memory) DRAM technology yesterday. I have known these were coming for a while but the thing that surprised me the most was the relatively reasonable cost for the performance that they deliver – at least, the relationship between cost and benefit of adding HBM to the system appears to be almost linear.
Posted in HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube
I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.
Posted in DDR3, DDR4, DIMM, DRAM Industry, Signal Integrity, Uncategorized
Graham Allan
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.