Posted by Marc Greenberg on November 19, 2014
I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.
If you’ve ever prototyped anything – whether it was a breadboard full of discrete devices, a piece of software, a demo board, or the first engineering sample chips to come out of the fab – it seems like the biggest problem is always making it work the very first time. A lot of the demo boards I’ve worked on have been equipped with a green LED that indicates the status and health of the board, and so the first objective is always “making the green light go on”.
It’s no different with FPGA prototyping; the very first goal is making the first test work – and this is something that is addressed very well with the IP prototyping kits.
Here is the problem that existed before IP prototyping kits: when prototyping a DDR subsystem, there are an almost infinite number of ways to configure it, and an almost infinite number of ways to do it wrong. Even if you take exactly what you have working in your ASIC RTL verification environment and port it over to an FPGA environment, you can still get it wrong, for lots of reasons that you might not even have thought of. The ASIC environment may have some “cheats” to make verification faster. The DDR memory device may be operating at a different frequency. You may have a different DDR memory device connected to your FPGA compared to what’s in the verification environment. There could be differences in how the memory controller and PHY in the FPGA are being programmed compared to the ASIC verification environment. Analog components may initialize differently ‘in real life” than they do in simulation. The design may not have been mapped from ASIC to FPGA correctly, for example, the signal pins you thought you connected to might not be the ones you actually connected to. There could be physical factors at work – are all the connectors seated correctly and is the power supply set up with the correct voltage?
If you get any one of these things wrong, you’ll likely be eyeballs-deep in user manuals, schematics, and helpdesk tickets. All of these factors and many more can conspire against you to prevent you from getting that first test working and “making the green light go on”.
Once you know that the whole setup works, that’s when you can start really working with it. You can run more tests, and you can make changes to the environment. You can start running your real software on it, and you can start finding the real issues that could affect the final design. Did you change something and the green light doesn’t go on anymore? Take a step back to the last known good point and debug your changes from there.
So this is where the new IP prototyping kit for DDR comes in. A full setup of the IP Prototyping kit for DDR would include:
– a pre-configured Synopsys uMCTL2 memory controller for use with the prototyping kit,
– a pre-configured FPGA emulation model of Synopsys’s Gen2 DDR multiPHY or DDR4 multiPHY that behaves similarly to the ASIC version while using FPGA resources,
– a HAPS DDR daughtercard,
– a reference design that includes an interface to an ARC Software Development Platform running software that is pre-installed with Linux drivers that can configure the controller and PHY registers and run DDR tests, and
– a windows-based GUI to allow easy manipulation of register settings in the IP Prototyping kit.
With all this equipment, we expect that you can unpack the box and get the first test running within minutes. Green light!!
Our customers have told us that without an IP prototyping kit, it can take as much as six weeks to get an FPGA prototype working (and you can bet it’s not a fun six weeks). Reducing the time taken to getting the first test running in a few minutes is a huge benefit to everyone on the project. Once you have the first test running, every other test you do is so much easier, because you have the confidence that the setup is correct and the results you are seeing – good or bad – are a result of what’s happening in your prototype and your software.
You can find out more about all the Synopsys IP prototyping kits at: http://news.synopsys.com/2014-11-19-Synopsys-Expands-IP-Accelerated-Initiative-with-New-DesignWare-IP-Prototyping-Kits-for-10-Interface-Protocols
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.