Posted by Marc Greenberg on August 20, 2014
Following today’s event in Seoul, there are still two more JEDEC LPDDR4 Workshops and Mobile Forums coming up in the next few weeks.
This Friday (August 22nd) there will be an event in Hsinchu, Taiwan, followed by the Santa Clara CA event on Sept 22-23.
Synopsys will be presenting “Using LPDDR4 Multi-Channel Architecture for Performance and Power” at the LPDDR4 workshops, being presented today (August 20) by HB Choi in Seoul, Friday by Tom Liu in Hsinchu, and on Sept 23 by me (Marc Greenberg) in Santa Clara.
Graham and I both plan to attend the Santa Clara event – please be sure to come by and say “Hi” and ask us any DDR questions you may have.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.