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Synopsys Announces Complete LPDDR4 IP Solution
Posted by Marc Greenberg on April 23, 2014
We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!
IP for LPDDR4 allows more chip designers to have access to LPDDR4 technology more quickly – even before the standard has been released. We’re big fans of LPDDR4 for it’s high bandwidth and low power features, and we see it as a technology that will make a huge difference to the performance and energy usage of mobile and consumer products of the next few years.
There has been a huge effort from the whole team here to develop all the pieces of the solution. There’s a formal press release here: http://news.synopsys.com/2014-04-23-Synopsys-Announces-Industrys-First-Complete-LPDDR4-IP-Solution-for-High-Performance-Low-Power-Mobile-SoC-Designs
Over the next little while we’ll go into details about what each part of this announcement means, but for this post let’s stick to the high points:
– An LPDDR4 multiPHY and I/Os with low power consumption
– An Enhanced Universal DDR Memory Controller (uMCTL2) with high bandwidth and low-power features
– LPDDR4 Verification IP
– Hardening and Signal Integrity services
All the parts of the solution will support speeds up to 3200Mbps per pin (25.6GBytes/s peak bandwidth for a typical 2-die LPDDR4 solution with 64 data pins) with low-power features, PoP or memory-down on PCB support, backwards compatibility with LPDDR3, DDR4, and DDR3/3L/3U memorie. All the parts of the solution are backed by Synopsys’s global team with 15 years of experience and more than 800 DDR Design IP wins to date.
We know you’ll have questions – please feel free to ask!
Marc Greenberg and Graham Allan
Graham Allan
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.