Posted by Marc Greenberg on January 2, 2014
Happy New Year to all our blog readers!
In fact, both companies’ press releases announced that they had developed the first 8Gb LPDDR4 device, which creates a question – who actually made the first one?
The answer to that question is likely known to a very small number of smartphone OEMs, but we can look at the data available to us to come close to an answer.
Firstly, a quick primer on LPDDR4:
– LPDDR4 is expected to be the follow-on DRAM memory to LPDDR3,
– LPDDR4 is expected to be used in high-end smartphones and tablets,
– LPDDR4 is expected to have double the bandwidth per pin of LPDDR3,
– LPDDR4 is expected to have a new 1.1v LVSTL I/O standard with a 350mV swing that should reduce power per bit transferred,
– LPDDR4 is expected to have 2 16-bit channels and 16 banks per die,
– JEDEC (the memory standards body) is working towards a published standard for LPDDR4 in 2014
Graham and I attend LPDDR4 standard task group meetings at JEDEC and we’re bound by confidentiality rules so I can’t make any definitive statements on the forthcoming standard beyond what’s already published online.
I can tell you that my private discussions with several smartphone chipmakers and OEMs last year indicated that they were expecting to receive LPDDR4 engineering samples from memory manufacturers in the first half of 2014. Those same smartphone chipmakers are already designing LPDDR4 interfaces into their next-generation smartphone chipsets. The press releases from Samsung and SK Hynix are totally believable in that context.
One might also ask, “Where is Micron in all this?” I searched the Micron website this morning for any LPDDR4 announcements and found none, however, that doesn’t mean that they’re not doing anything. As one of the three largest DRAM manufacturers, and with a relatively small number of first adopters for LPDDR4 devices, Micron may be marketing directly to their customers instead of making press releases. Having said that, Micron have added LPDDR4 parts to their part numbering scheme and created part numbers for speeds up to 2133MHz (4266Mbps data rate or 17GByte per second per die). Dan Skinner from Micron made an excellent presentation on LPDDR4 at the JEDEC Mobile Memory Forum in May 2013. You may draw your own conclusions.
Now let’s break down what was actually announced in each of the Samsung and SK Hynix press releases.
|What was announced||Samsung||SK Hynix|
|Development schedule||“…developed the industry’s first eight gigabit (Gb), low power double data rate 4 (LPDDR4), mobile DRAM…”||“…developed the world’s first 8Gb(Gigabit) LPDDR4(Low Power DDR4)…”|
|DRAM Speed||“…the LPDDR4 chip will enable a data transfer rate per pin of 3,200 megabits per second (Mbps)…”||“This new product works at 3200Mbps…”|
|Process Technology||20nm class||20nm class|
|Availability||“…will provide its new 8Gb LPDDR4 DRAM in 2014…”||“The new interface LPDDR4 is expected to be loaded onto flagship mobile devices at the end of 2014…”|
So we can see the press releases are quite similar. Hynix announced that they’re “providing the samples of LPDDR4 to major customers”. Separate from this press release, the advance program for ISSCC in February 2014 includes a paper from Samsung on a 1.0v 3200Mbps LPDDR4 device indicating progress to reduce the I/O voltage from 1.1v to 1.0v and a core voltage reduction to under 1v.
So which of the three major DRAM manufacturers was actually first to have a working LPDDR4 device in their lab? We may never know. Who delivered the first LPDDR4 engineering sample to a smartphone chipset maker or OEM is only known to a handful of those customers. What’s important is that LPDDR4 is clearly coming and you should consider whether LPDDR4 makes sense for your next product. If you’re starting a new chip design that uses DRAM, you should ask Synopsys how we can help you succeed with LPDDR4 and other high-speed interfaces.
— Marc Greenberg
This post was edited to provide more obvious links to the Samsung and SK Hynix press releases.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.