Posted by Marc Greenberg on October 24, 2013
I’m going to very occasionally use this blog to talk about my products, especially when I have a new product to talk about.
Yesterday we the released the latest revision of our Universal Memory Controller 2 Design IP – “uMCTL2” revision 2.20a.
uMCTL2 supports all the popular DDR DRAM standards, like DDR3, DDR4, LPDDR2 and LPDDR3. The last revision, uMCTL2 2.10a, added true Quality of Service (QoS) support, AMBA AXI4 and an Improved Low-Power Interface.
uMCTL2 revision 2.20a adds many new features targeted in four main areas: Extended DDR4 features, DIMM Improvements, New RAS (Reliability, Availability, Serviceability) Features, and more QoS Improvements. Over the next few weeks I’ll blog some more details of the system-level issues that these new features address.
As always, you can find out more about uMCTL2 on the Synopsys website or by submitting a “Contact Us” form.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.