By now you have probably seen the TV commercials showing the latest model vehicles that can automatically initiate braking when they detect a collision is imminent. Technologies like this are known as “Advanced Driver Assistance Systems” (ADAS).
As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.
AMD announced their new line of GPUs are using the new HBM (High Bandwidth Memory) DRAM technology yesterday. I have known these were coming for a while but the thing that surprised me the most was the relatively reasonable cost for the performance that they deliver – at least, the relationship between cost and benefit of adding HBM to the system appears to be almost linear.
I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.
Samsung has posted their DDR4 product guide on their website, and it gives us excellent insight into the direction that Samsung plans to go with DDR4 in the next few months with a lot of data that wasn’t previously publicly available.
JEDEC officially published the LPDDR4 standard today. It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication. That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market. The JEDEC committees responsible for this latest publication should be very proud of their achievement. Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.
A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course. One thing is certain; the future will not be an easy path for DRAMs. The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies. After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment. Unfortunately, that something else will likely be “somethings” else. Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.