By now you have probably seen the TV commercials showing the latest model vehicles that can automatically initiate braking when they detect a collision is imminent. Technologies like this are known as “Advanced Driver Assistance Systems” (ADAS).
People are sometimes surprised when I tell them that more than $40 Billion of DRAM chips are sold every year – but have you ever wondered where they all go?
As reported by Chipworks last week, the Apple iPhone 6S is using 2GB of LPDDR4 DRAM. This means that Apple is now joining other phones such as the LG Gflex2, the Samsung Galaxy S6, Xiaomi Mi Note Pro, HTC OneM9, and several others in using LPDDR4 RAM.
There was a huge technology announcement on 3D XPoint(tm) technology about 3 weeks ago – but without many details. I’m at the IDF2015 conference in San Francisco this week and we learned a lot more.
AMD announced their new line of GPUs are using the new HBM (High Bandwidth Memory) DRAM technology yesterday. I have known these were coming for a while but the thing that surprised me the most was the relatively reasonable cost for the performance that they deliver – at least, the relationship between cost and benefit of adding HBM to the system appears to be almost linear.
Our friends in Synopsys’s Verification Group have been putting together an excellent set of Memory Verification IP (VIP) for DDR4, DDR3, LPDDR4, LPDDR3, that complements our other VIP for Flash, MIPI, PCIe, AMBA, Ethernet, HDMI, SATA, etc…
Samsung made a big event of the launch of the Galaxy S6 today (April 10th, 2015) making the S6 and S6 Edge available at multiple US and international retailers simultaneously. The Galaxy S6 is based around Samsung’s own Exynos 7420 application processor and LPDDR4 DRAM.
I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.
I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.
A good friend of mine alerted me that Dell’s latest product lines featuring DDR4 memory are scheduled to ship as early as next week. A quick summary:
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.