Breaking The Three Laws

Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.

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I ran into the article below titled Emulation vs. Prototyping.

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This weeks blog can be found here: https://blogs.synopsys.com/tousbornottousb/2016/02/12/will-usb-type-c-burn-my-device/

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In a continuation of last week’s blog titled “Validating USB Type-C using Physical Prototyping” one of the key USB folks here at Synopsys, Morten Christiansen, made a short 30 second video of the DesignWare USB Type-C physical prototype in action. (Click the picture to take you to the video)

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This week Synopsys Introduced the DesignWare USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection. USB has been continually evolving and USB Type-C is the one cable to connect them all. The USB Type-C is already gaining widespread acceptance and is becoming the most rapidly adopted USB standard in history. The need to rapidly adopt a new standard comes with challenges for the design engineers, verification team and the software developers.

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I visited the Synopsys offices again this week and sat down with a couple of the R&D engineers to discuss what our customers should expect in respect to performance when they utilize the new HAPS-80 and HAPS ProtoCompiler. I blogged about this a while back, I now have the latest information.

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It’s been about a year that I have been blogging on the new Xilinx UltraScale VU440 FPGA devices and Xilinx is finally shipping production devices. I say finally not because they are late, they are actually shipping exactly as communicated, but finally due to the pent up demand for systems utilizing these large prototyping capable devices is bursting at the seams. Synopsys is shipping hundreds of systems to deliver on our backlog.

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Happy New Year and all that. What an fantastic 2015 for physical prototyping and I expect 2016 to be even better now the Xilinx UltraScale based solutions are rolling out. Of course the highlight of the work year for me was the launch of the HAPS-80 with ProtoCompiler.

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Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

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While traveling this week I found myself explaining the value of Hybrid Prototyping when used with DesignWare IP or your own IP blocks and RTL code. Simply put, using Hybrid Prototyping you can immerse the IP in the context of the SoC without needing to have RTL for the whole SoC. Hybrid Prototyping enables a Pre-RTL SoC representation to be rapidly created (using off the shelf Virtualizer Development kits as a starting point) and incorporating the block(s) under test modeled in HAPS Physical Prototype. This Hybrid Prototype is used for early software development in the case of the DesignWare IP and can be used in the same way for your own blocks in addition to increasing the verification of the design(s) under test.

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