Breaking The Three Laws

Archive for the 'Uncategorized' Category


Partitioning Poser #1

There are those who say that one should partition so that only sequential eements are allowed to appear at the FPGA edges, thus simplifying the timing and constraints at the FPGA pins.

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Posted in Uncategorized |


I love DAC, honest, I really do

Dear reader, With DAC just around the corner, those planning to attend are probably already calculating their optimal route through the maze of booths, panels, papers and of course the parties. FPGA-based prototyping is likely to have its strongest DAC ever, and Synopsys is doing its bit to carry on the good work.

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Posted in ASIC Verification, FPGA-Based Prototyping, Getting Started, Uncategorized |