Which is your favorite FPGA-based prototyping setup?
Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards,
Posted in Admin and General, HAPS-80, Support, UltraScale
Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes
I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)
Posted in ASIC Verification, Bug Hunting, Debug, FPGA-Based Prototyping, HAPS-70, HAPS-80, Man Hours Savings, Performance Optimization, Real Time Prototyping, Tips and Traps, UltraScale
Verifying Power Management Modes, both Software and Hardware
Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!”
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation, UltraScale, UPF, Use Modes
ESD Precautions Essential for prototype handling
Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape.
Posted in Admin and General, HAPS-80, UltraScale
It’s not too late to attend SNUG Silicon valley
Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx
Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes
What’s in it for me? The market shift to integrated Physical Prototyping
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes
Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities
Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale
Results from Xilinx UltraScale VU440 based HAPS-80 with HAPS ProtoCompiler
I visited the Synopsys offices again this week and sat down with a couple of the R&D engineers to discuss what our customers should expect in respect to performance when they utilize the new HAPS-80 and HAPS ProtoCompiler. I blogged about this a while back, I now have the latest information.
Posted in UltraScale
Xilinx UltraScale VU440 FPGA Production Devices Finally Available
It’s been about a year that I have been blogging on the new Xilinx UltraScale VU440 FPGA devices and Xilinx is finally shipping production devices. I say finally not because they are late, they are actually shipping exactly as communicated, but finally due to the pent up demand for systems utilizing these large prototyping capable devices is bursting at the seams. Synopsys is shipping hundreds of systems to deliver on our backlog.
Posted in UltraScale
Prototyping Low Power Functions Using UPF
Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.
Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.