Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!” BTW: This blog was inspired by a true story of a challenge that Achim Nohl, Technical Marketing Manager for HAPS Physical Prototyping recently experienced: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=51543 Power management is an increasingly complex function provided by hardware and controlled by a […]
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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation, UltraScale, UPF, Use Modes | Comments Off on Verifying Power Management Modes, both Software and Hardware
Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx Prototyping topics: Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System FPGA Debug: Improving Debug Turnaround Time in High Speed Designs Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution Adapt, Port, and Integrate Quickly – Prototyping the Right Way Address TTM by Prototyping […]
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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes | Comments Off on It’s not too late to attend SNUG Silicon valley
FPGA-based physical prototyping is the go-to standard for high-performance, high-productivity verification, debug, and software development on many electronic systems today. But, it is becoming increasingly difficult to put together an ad-hoc prototype mixing pieces from various vendors with home-grown components. With the complexity of today’s systems, an integrated prototyping system can bring significant advantages. Learn […]
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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off on What’s in it for me? The market shift to integrated Physical Prototyping
Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which […]
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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale | Comments Off on Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities
Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process. Click here for the full article To SUBSCRIBE use the Subscribe link in the left hand navigation bar. Another option to subscribe is as […]
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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off on Q&A Using FPGA Prototypes for Software Development & More
This week Synopsys Introduced the DesignWare USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection. USB has been continually evolving and USB Type-C is the one cable to connect them all. The USB Type-C is already gaining widespread acceptance and is becoming the most rapidly adopted USB […]
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Posted in ASIC Verification, Bug Hunting, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Project management, System Validation, Use Modes | Comments Off on Validating USB Type-C using Physical Prototyping
Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was […]
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Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes | Comments Off on Prototyping Low Power Functions Using UPF
I ran across this blog on Imaginations website which covers details on prototyping the PowerVR Series6XT on HAPS: http://blog.imgtec.com/powervr/prototyping-a-powervr-series6xt-gpu-using-an-optimized-flow-from-synopsys I highly recommend reviewing the material as it provides insight into not only how to prototype large GPU’s but also how to quickly scale multi-FPGA prototypes. Short blog this week as I’m off to do a […]
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Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off on Prototyping a PowerVR Series6XT GPU using an optimized flow from Synopsys
Recently at SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology […]
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Posted in ASIC Verification, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Project management, System Validation, Technical, Tips and Traps, Use Modes | Comments Off on Intel’s FPGA-Based Prototyping presentations from SNUG Israel
The myths of FPGA-based prototyping are still being proliferated and I have taken on a quest to educate the world on what FPGA-based prototyping really delivers. The latest myth propagation is seen below and was cut from a recent posting on a well-known industry website. You are all smart, you will be able to work […]
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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, Performance Optimization, System Validation, Use Modes | Comments Off on Expectation setting for FPGA-based prototyping
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.