Breaking The Three Laws

Archive for the 'Performance Optimization' Category

 

Exploratory Place and Route improves timing by up to 10%

This week I am going to discuss a new and unique capability in the Synopsys FPGA/FPGA-based prototyping tools that get you the double whammy, helps solve FPGA routing congestion and improves FPGA performance. The new capability is called Exploratory place and route (PAR). Oh, before I forget I’m off on vacation for a week so no blog next week. I know this is going to break my posting flow and even though FPGA-based prototyping is always on my mind even when I’m hiking or snorkeling or kayak surfing or just sitting on the beach relaxing, I’m going to resist the urge to post by not traveling with my laptop.

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Posted in Performance Optimization, Use Modes |

 

Intel’s FPGA-Based Prototyping presentations from SNUG Israel

Recently at  SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology guide so I highly recommend you review the material.

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Posted in ASIC Verification, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Project management, System Validation, Technical, Tips and Traps, Use Modes |

 

Highest Performance Xilinx UltraScale-based Prototypes

While individually the Xilinx UltraScale VU440 devices deliver increase performance, Xilinx quotes the (-1) speed grade having the same logic performance as the Xilinx Virtex-7 2000T (-2) speed grade, this unfortunately has very little effect on multi-FPGA prototype performance. The reason is that the performance bottleneck is not the speed of the logic in the FPGA device itself, it’s the overall multi-FPGA interconnectivity, we like to call this the pin-multiplexing bottleneck. Take the simple example below where an SoC is partitioned across multiple FPGA’s.

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Posted in Performance Optimization, UltraScale |

 

Expectation setting for FPGA-based prototyping

The myths of FPGA-based prototyping are still being proliferated and I have taken on a quest to educate the world on what FPGA-based prototyping really delivers. The latest myth propagation is seen below and was cut from a recent posting on a well-known industry website. You are all smart, you will be able to work out where it comes from. Fun read.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, Performance Optimization, System Validation, Use Modes |

 

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM…. Yes, we did this way back in 2010 with the launch of the HAPS-60 complete solution, and then raised the bar in 2012 with the launch of the evolutionary HAPS-70 complete solution. Synopsys HAPS is a proven integrated solution delivering the fastest time to operational prototype, highest system performance, superior debug and advanced capabilities including Hybrid Prototyping and global server farm access.

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Posted in Admin and General, ASIC Verification, Bug Hunting, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Real Time Prototyping, Support, System Validation, Use Modes |

 

Reduce WNS by up to 60%, sometime more

The WNS I am talking about is Worst Case Negative Slack and not White Nose Syndrome, a disease in North American bats which, as of 2012, was associated with at least 5.7 million to 6.7 million bat deaths. Please help and stop the spread of this nasty disease. Poor little bats have no defense against it. The WNS I’m going to talk about is Worst Case Negative Slack of a prototyping design, reduce WNS and prototype execution performance increases.

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Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Performance Optimization, Project management, System Validation, Use Modes |