Breaking The Three Laws

Archive for the 'Milestones' Category

 

Part Deux: How many ASIC Gates does it take to fill an FPGA?

Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.

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Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes

 

How many ASIC Gates does it take to fill an FPGA?

How many ASIC Gates does it take to fill an FPGA?

Continue Reading...

Posted in Man Hours Savings, Milestones, Project management