This weeks blog can be found here: https://blogs.synopsys.com/tousbornottousb/2016/02/12/will-usb-type-c-burn-my-device/
The WNS I am talking about is Worst Case Negative Slack and not White Nose Syndrome, a disease in North American bats which, as of 2012, was associated with at least 5.7 million to 6.7 million bat deaths. Please help and stop the spread of this nasty disease. Poor little bats have no defense against it. The WNS I’m going to talk about is Worst Case Negative Slack of a prototyping design, reduce WNS and prototype execution performance increases.
Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Performance Optimization, Project management, System Validation, Use Modes |
Let me be the last to wish you “Happy New Year” and all that….
With it being USA Thanksgiving last week you would think I would have relaxed but I must say I’ve been very busy finishing off a couple of projects. So this week’s blog is on these my latest projects.
Posted in Mick's Projects |
It’s the age old question, what came first, the chicken or the egg?
We are seeing PCIe Gen3 being integrated into many different types of SoC’s. The above summarizes the changes we are seeing in the market across 2013 and 2014. One notable area is that PCIe is moving into enterprise storage with PCIe being used for the interface to NAND flash storage devices. The below picture shows the key needs in the segments. PCIe Gen 3 is a great fit for storage as it offers 8Gb/s transport rate across a single lane with x2, x4, x8, x16 lane configurations resulting in huge bandwidth potential. My thanks to Scott Knowlton, of the Express Yourself Blog for the PCIe market data and segment analysis
It’s was a short week for me with Memorial day on Monday and the I took Thursday off to play at the race track. Next week is DAC so if you happen to be visiting make sure you drop past the Synopsys booth and say hello. I’m only attending DAC on Monday so don’t miss out, maybe I’ll buy you a cup of coffee or something.
Posted in Mick's Projects |
Achieving first pass silicon success is always the goal of the project. While a company may plan for a second chip spin they really want first pass silicon success enabling reduced cost and earlier time to market. I ran across this video featuring Peraso and Eric from the DesignWare USB team, http://youtu.be/DyNyZP8Ysj4 . Now while Peraso do not claim first pass success bringing up a chip in the lab in 24 hours is amazing. Peraso used HAPS FPGA-based prototypes for system validation enabling them to test their software with their RTL implementation before they taped out. As you can tell from the video, Peraso were very, very happy with the fact that they had the silicon up and running in such a short period.
Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, Milestones, Project management, Real Time Prototyping, System Validation |
Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Project management, System Validation, Technical |
My blog on prototyping last week was huge and I have been told people are still reading it, as in they started last week and they have yet to make it to the end. This week’s blog should be nice and short and mostly off-topic.