While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:
Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx
Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes
Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.
Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes
Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.
While traveling this week I found myself explaining the value of Hybrid Prototyping when used with DesignWare IP or your own IP blocks and RTL code. Simply put, using Hybrid Prototyping you can immerse the IP in the context of the SoC without needing to have RTL for the whole SoC. Hybrid Prototyping enables a Pre-RTL SoC representation to be rapidly created (using off the shelf Virtualizer Development kits as a starting point) and incorporating the block(s) under test modeled in HAPS Physical Prototype. This Hybrid Prototype is used for early software development in the case of the DesignWare IP and can be used in the same way for your own blocks in addition to increasing the verification of the design(s) under test.
Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.
Back in 2011 I had a vision, a vision for how users of both IP and FPGA-Based Prototypes could be more productive. The problems these users faced was not to do with bugs or lack of capabilities in the products but from the fact that the usage crossed between the two products. IP users traditionally are not experienced prototypers and prototypers lacked IP specific knowledge. Of course this was not helped by the fact that the IP did not document it’s prototyping specific needs. For example, the IP is optimized for ASIC deployment and when you prototype it the clocking, reset and rams sometimes need to be modified to fit into a FPGA environment. Another issue is that as it’s ASIC IP not all configurations can be physically supported in FPGA. For example while the IP might support up to 16 IO ports on the prototype you might only be physically implement up to 4.
I ran across this blog on Imaginations website which covers details on prototyping the PowerVR Series6XT on HAPS: http://blog.imgtec.com/powervr/prototyping-a-powervr-series6xt-gpu-using-an-optimized-flow-from-synopsys
Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes