Synopsys’ big press this week from DAC was the announcement of the IP Accelerated initiative. As this initiative combines Synopsys’ leading interface IP, DesignWare, HAPS FPGA-Based Prototyping systems and Virtual Development Kits as you might guess I have been very involved in this evolutionary development. I executed my own personal top secret testing of the deliverables, more on that later in this blog. I’m so happy that we have finally made this initiative public as I have really wanted to talk about it.
While at SNUG in England I had the pleasure of being one of the first people on the planet, yes planet, to see the demonstration of the Imagination PowerVR Series 6XT running at speed on HAPS. The demonstration streamed video data from a host to DDR3 on the HAPS system via a PCIe connection. This video data is then manipulated via the GPU and output in real time to DVI for display on a monitor. The demonstration was very impressive and eye catching to anyone who reviewed it. Imagination internally developed this setup to do what they call DriverLive software development as well as be able to run the 1000’s of GPU compliance tests in a matter of hours thanks to the high performance operation.
My blog on prototyping last week was huge and I have been told people are still reading it, as in they started last week and they have yet to make it to the end. This week’s blog should be nice and short and mostly off-topic.
Last week over a lunch break, rather than relaxing or even eating I decided to create some fun HAPS desk ornaments to brighten up my office. I had run across this nice little App called Foldify http://www.foldifyapp.com/ It’s a great little app that enables you draw, create and paste images onto blank flat forms. You then print them out and fold them on the dotted lines. I then sent the ones I created to my team and management so they too could enjoy these desktop fun creations.
A couple of folks complained that my last blogs have been a bit long and boring. (Boring! Me?) So I would like to start this week and apologize to all my 5th Grade readers, I’ll try harder in the future to use smaller words and more pictures.
Of course I am talking about the MIPI protocols and not something you can catch from too much internet. I’ve blogged about MIPI and FPGA-based prototyping before but I felt it was time to talk about MIPI again as it’s exploding all over the mobile market. In addition to the well know MIPI specifications for Camera and Display interfaces, CSI and DSI you now have UFS for mass storage, High Speed Synchronous, Low latency, Peripheral interface and the list goes on.
Hot on the heels of last week’s blog on the common mistakes first time prototypers make, Synopsys published a white paper titled “My RTL is an Alien!”.
FPGA-based prototypes offer tremendous value for system-on-chip validation and hardware/software integration by delivering high capacity, fast clock performance, and real-world I/O connectivity. The combination of performance and high-fidelity makes software integration and development tasks feasible months before test silicon is available. But when something goes wrong, debugging a complex prototype can be challenge.
In my final installment on RTL Block Validation we are going to talk about the Hybrid Prototyping usage case.
Continuing on my theme of RTL Block/IP validation I wanted to discuss the most popular and typically the most well understood usage mode, Standalone.