Breaking The Three Laws

Archive for the 'HAPS-80' Category

 

Which is your favorite FPGA-based prototyping setup?

Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards,

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Posted in Admin and General, HAPS-80, Support, UltraScale |

 

Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)

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Posted in ASIC Verification, Bug Hunting, Debug, FPGA-Based Prototyping, HAPS-70, HAPS-80, Man Hours Savings, Performance Optimization, Real Time Prototyping, Tips and Traps, UltraScale |

 

ESD Precautions Essential for prototype handling

Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape.

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Posted in Admin and General, HAPS-80, UltraScale |

 

It’s not too late to attend SNUG Silicon valley

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes |

 

What’s in it for me? The market shift to integrated Physical Prototyping

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes |

 

Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale |

 

Q&A Using FPGA Prototypes for Software Development & More

Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes |

 

Prototyping Low Power Functions Using UPF

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

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Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes |

 

LAST CHANCE TO VOTE: ARM TechCon Innovation Challenge 2015 – Vote for HAPS-80 FPGA-Based Prototyping System

LAST CHANCE TO VOTE: The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system

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Posted in HAPS-80, UltraScale |

 

ARM TechCon Innovation Challenge 2015 – Vote for HAPS-80 FPGA-Based Prototyping System

The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system

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Posted in HAPS-80, UltraScale |