Breaking The Three Laws

Archive for the 'Tips and Traps' Category

 

The Secret Ninja-Fu for Higher Performance Prototype Operation

Not many people know this but I am a FPGA-based prototyping Ninja-Fu master. What super power do I have you ask? I have the power to enable higher performance prototype operation and in this week’s blog I am sharing this ancient secret power with you. Wow, the start of this blog sounds like the bio from a really bad “B” movie, it definitely seemed funnier in my mind, then again everything seems funnier in my mind. There is actually some seriousness to this blog as I really am going to share the not so secret method to enable higher performance in your FPGA-based prototypes.

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Posted in Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Mick's Projects, System Validation, Technical, Tips and Traps |

 

Prototyping wearables and the Internet of Things (IoT)

Is this the future of wearable technology?

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Posted in ASIC Verification, FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps |

 

Reducing Risk with Pre-Silicon Demonstrations

This week’s blog is going to show you how FPGA-based prototyping delivers a whole new level of WOW factor to a new product introduction. Oh, and this also sends a message of reduced risk to the prospect customer. OK, so here we go, recently Synopsys announced the industry’s first USB Superspeed 3.1 10 Gb/s platform to platform, host to device, data transfer demonstration. Here is a link to the news release.

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Posted in FPGA-Based Prototyping, Tips and Traps |

 

FPGA-Based Prototyping Best of the Best

As it’s my first blog of 2014 (Happy New year and all that) I wanted to reflect back on 2013 and what better way to do that than review the best of the best of my blog postings from 2013. So drum roll please… here is my short list of cracking blog posts from 2013 in chronological order. This is not a list of all the blogs (but it did turn out to be a big list) just the ones that I personally think have the most valuable FPGA-based prototyping information.

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Posted in Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Technical, Tips and Traps |

 

Command and Control

It’s been a quiet week for me and prototyping but I did talk to an engineer about command and control of an FPGA-based prototype which I thought was quite interesting I will share the story.

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Posted in FPGA-Based Prototyping, Mick's Projects, Tips and Traps |

 

Prototyping Cutting Edge Standards – 10G USB 3.1 Host and Device

As we all know FPGA-based prototyping enables early software development, HW/SW integration and system validation but did you also know that HAPS FPGA-based prototyping is also designed to make Eric Huang, PMM for USB IP at Synopsys famous? I’ll be honest, when we designed the HAPS-70 systems we did not highlight this as part of the MRD which shows that sometimes capabilities evolve on their own.

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Posted in ASIC Verification, FPGA-Based Prototyping, In-System Software Validation, Tips and Traps |

 

Superior debug visualization and efficiency

I noticed that Synopsys launched the new Verdi3 which provides the capability to debug both the hardware RTL code and the Software C code. Here is a video demo of the new capabilities: http://www.synopsys.com/Tools/Verification/debug/Pages/verdi-hw-sw-debug-video.aspx

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Posted in ASIC Verification, Debug, FPGA-Based Prototyping, Tips and Traps |

 

Do you use a hammer to put in a screw?

This week I was asked to compare the Synopsys HAPS systems to FPGA vendor evaluation boards. I only have good things to say about the FPGA vendor evaluation boards but when comparing these evaluation boards to HAPS for serious FPGA-Based Prototyping I just said, “That’s like using a hammer to put in a screw”. A hammer is a great tool but it’s not the right tool for the job. Evaluation boards are not designed with FPGA-Based prototyping in mind, they are designed to enable evaluation of the individual FPGA devices capabilities. “Evaluation” board, not FPGA-based prototyping system. HAPS is architected with the FPGA-based prototyping in mind and provides the capabilities to increase the customer’s productivity. Our goal is to improve the customer’s efficiency by providing out-of-the-box capabilities which the customers can deploy immediately. To meet the demands of FPGA-based prototyping the customer would need to hand craft such capabilities for an evaluation board and then internally support it’s usage which detracts the customer from the important tasks such as early software development, hw/sw integration and creating product differentiation.

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Posted in FPGA-Based Prototyping, Tips and Traps |

 

Invaders from Space: My RTL is an Alien!

Hot on the heels of last week’s blog on the common mistakes first time prototypers make, Synopsys published a white paper titled “My RTL is an Alien!”.

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Posted in ASIC Verification, FPGA-Based Prototyping, Getting Started, Humor, Technical, Tips and Traps |

 

Do you have what it takes to be a prototyping super hero?

I was recently talking to a customer who found that deploying FPGA-based prototyping was a challenge. This was a customer who had only every done simulation for verification purposes. Their last chip incorporated dual embedded processors and unfortunately they had to re-spin the silicon due to a hardware bug that they found only when running the real software. This bug was devastating, the cost was huge as it included the physical costs of the re-spin but worst was the revenue hit from being late to market. This company knew it had to adopt FPGA-Based Prototyping to enable early software development, HW/SW integration and System Validation all PRE-SILICON. The goal was to run the actual software against the hardware and identify HW/SW bugs before code freeze and tape-out.

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Posted in ASIC Verification, Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Project management, Technical, Tips and Traps |