I was recently talking to a customer who found that deploying FPGA-based prototyping was a challenge. This was a customer who had only every done simulation for verification purposes. Their last chip incorporated dual embedded processors and unfortunately they had to re-spin the silicon due to a hardware bug that they found only when running the real software. This bug was devastating, the cost was huge as it included the physical costs of the re-spin but worst was the revenue hit from being late to market. This company knew it had to adopt FPGA-Based Prototyping to enable early software development, HW/SW integration and System Validation all PRE-SILICON. The goal was to run the actual software against the hardware and identify HW/SW bugs before code freeze and tape-out.
Guest Blog Alert – Doug Amos, author of the FPGA-based Prototyping Methodology.
This week we are going to talk about the PCIe connected prototype for RTL block and IP validation and again discuss the benefits of using the loop concept.
I’m presenting at the quarterly GSA Intellectual Property (IP) Working Group Meeting this morning and while reviewing my slides I thought I would blog on a couple of aspects of IP (RTL blocks) and IP to SoC Prototyping. I’ve blogged on this topic before but it was ages ago and even I’ve forgotten what I spoke about.
At the recent SNUG UK Paul Robertson from Broadcom presented a paper on their use of FPGA-Based Prototyping for their current generation of SoC’s. For those with Synopsys SolvNet access the paper can be found by following this link: http://www.synopsys.com/news/pubs/snug/2013/uk/C1_Robertson_pres.pdf
My wife’s nickname for me is “More Power Mick” and as I am doing a blog on UPF and validating it as part of an FPGA-based prototyping flow I thought sharing this nickname was relevant.
Last week I wrote almost nothing about FPGA-Based Prototyping because I was off in the weeds talking about painting fish and my Subaru building and racing hobby (Some says it’s an obsession, not a hobby). I got so many complements on my blog, thanks! This week it’s back to your normally scheduled programming. I was planning a short blog posting this week but then I got carried away and now I find this post really long. Stick it out and read the whole thing it’s full of useful tips.
Following up from last week’s blog I was asked what I thought were the main technical selection criteria for an FPGA-based prototyping platform. I thought hard and long (~5 seconds) and said Capacity, Performance and Ease of use. The reasoning behind capacity being #1 is that you need a platform that has sufficient capacity to cater for your current project requirements including catering for design size growth over the course of the project. You then also want to select a platform that can be reused across multiple projects increasing your return on investment. If the platform does not provide sufficient capacity for the design then you don’t leave the starting gate.
Wow, the free ebook download of the FPGA-based Prototyping Methodology Manual has surpassed 3500 downloads. The PDF version has been downloaded over 2800 times in addition to the Epub and Kindle version at over 500 times each.
One of my motto’s is “never let good whiteboard art go to waste” which prompted this blog posting. I should note that I am well known for my graphical skills, actually my lack of color matching skills has resulted in eyes burning and people running from my presentations screaming. (Honest, no joke!)