Breaking The Three Laws

Archive for the 'FPGA-Based Prototyping' Category

 

Part Deux: How many ASIC Gates does it take to fill an FPGA?

Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.

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Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes

 

HT 3 Connector Utilization Recommendation

I snapped off the picture of the HAPS-70 system below at a recent customer meeting and it gave me the idea for this blog. Other than the fact that the systems look “well sexy” (Yes, usually a term you do not hear used to describe hardware) this picture also highlights the flexible nature of the system interconnect architecture with the high performance coax cables and recommended usage.

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Posted in FPGA-Based Prototyping, Getting Started, Tips and Traps

 

Is it Emulation or FPGA-Based Prototyping that I want?

Question: Is it Emulation or FPGA-Based Prototyping that I need for my project?

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Posted in FPGA-Based Prototyping, Tips and Traps

 

Keeping Your RTL Clean: Part 2

Hi Prototypers,

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Posted in FPMM Methods, Uncategorized