Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.
Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes
I snapped off the picture of the HAPS-70 system below at a recent customer meeting and it gave me the idea for this blog. Other than the fact that the systems look “well sexy” (Yes, usually a term you do not hear used to describe hardware) this picture also highlights the flexible nature of the system interconnect architecture with the high performance coax cables and recommended usage.
Posted in FPGA-Based Prototyping, Getting Started, Tips and Traps
Question: Is it Emulation or FPGA-Based Prototyping that I need for my project?
Posted in FPGA-Based Prototyping, Tips and Traps
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.
