Breaking The Three Laws

Archive for the 'Daughter Boards' Category

 

It’s not too late to attend SNUG Silicon valley

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes |

 

Video: Using HAPS to Verify DesignWare USB Type-C IP Functionality

In a continuation of last week’s blog titled “Validating USB Type-C using Physical Prototyping” one of the key USB folks here at Synopsys, Morten Christiansen, made a short 30 second video of the DesignWare USB Type-C physical prototype in action. (Click the picture to take you to the video)

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Posted in Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Milestones, Real Time Prototyping |

 

Validating USB Type-C using Physical Prototyping

This week Synopsys Introduced the DesignWare USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection. USB has been continually evolving and USB Type-C is the one cable to connect them all. The USB Type-C is already gaining widespread acceptance and is becoming the most rapidly adopted USB standard in history. The need to rapidly adopt a new standard comes with challenges for the design engineers, verification team and the software developers.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Project management, System Validation, Use Modes |

 

Success Prototyping with UltraScale VU440 devices

It’s been a while since Xilinx shipped the first UltraScale VU440 engineering sample devices to Synopsys so I thought it time to deliver a short update on development progress. It might be hard to see in the above but that is a picture of one of the new development HAPS systems for the UltraScale VU440 devices. I say hard to see not only as the picture quality is low but also because we have the system completely configured with intelligent interconnect as part of our stringent characterization and functional validation process.

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Posted in Admin and General, ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Project management, Real Time Prototyping, System Validation, UltraScale, Use Modes |

 

Fight Club: Automated vs. Hand Crafted Pin Multiplexing

This week a prototyping engineer challenged me that “his” customized and hand crafted pin multiplexing capability was “better” than the HAPS High Speed Time-Domain Multiplexing, HSTDM. My response, “Faster, maybe, better NO”. This blog explains why the HAPS HSTDM capability will beat out a custom coded multiplexing capability hands down every time.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, Project management, Support, Use Modes |

 

Prototyping at the Consumer Electronics Show, CES

Let me be the last to wish you “Happy New Year” and all that….

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Posted in Daughter Boards, DWC IP Prototyping Kits, FPGA-Based Prototyping, Getting Started, Humor, Mick's Projects |

 

Recap of what you missed, impactful blogs from the last 3 months

During a customer meeting last week I found myself explaining many different topic’s all of which I have blogged about over the last couple of months. I suddenly realized that while I blog every week that many of you might not get time to read them every week and miss important information. Below is a list of what I think are the impactful blogs from the last couple of months, just in case you missed them.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, IP Validation, Man Hours Savings, Use Modes |

 

SW Dev Env using ARM-based daughter board directly vs. Hybrid Prototype

This week’s blog is a bit of a mashup (Yes that is a real word, a mashup, in development, is something that uses content from more than one source to create a single new offering) as I am pulling together two topics to create one. The #1 usage case of prototyping is for early software development. You can do this very early, pre-RTL using Virtual Prototypes, later in the design cycle with FPGA-based Prototypes but it’s the bit in the middle that this week’s blog examines.

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Posted in ASIC Verification, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, IP Validation |

 

Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09

Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09, starting in reverse order this week.

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Posted in Daughter Boards, Man Hours Savings, Use Modes |

 

Top 3 Myths of FPGA-based prototyping BUSTED

This week I’ve spent most of my time busting the top three myths of FPGA-Based Prototyping, specifically in respect to the HAPS solution based. The top 3 are:-

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, Man Hours Savings |