Breaking The Three Laws

Archive for the 'Bug Hunting' Category

 

Would you like 2X Performance AND Reduced Tool Runtime (Turn-around-Time)?

Above is a picture of HAPS High Speed Time Domain Multiplexing (HAPS HSTSM) being tested across the current HAPS-70 and the new HAPS systems based on Xilinx UltraScale FPGA devices.

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Posted in Bug Hunting, Man Hours Savings, Performance Optimization, Project management, UltraScale |

 

Expectation setting for FPGA-based prototyping

The myths of FPGA-based prototyping are still being proliferated and I have taken on a quest to educate the world on what FPGA-based prototyping really delivers. The latest myth propagation is seen below and was cut from a recent posting on a well-known industry website. You are all smart, you will be able to work out where it comes from. Fun read.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, Performance Optimization, System Validation, Use Modes |

 

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM…. Yes, we did this way back in 2010 with the launch of the HAPS-60 complete solution, and then raised the bar in 2012 with the launch of the evolutionary HAPS-70 complete solution. Synopsys HAPS is a proven integrated solution delivering the fastest time to operational prototype, highest system performance, superior debug and advanced capabilities including Hybrid Prototyping and global server farm access.

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Posted in Admin and General, ASIC Verification, Bug Hunting, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Real Time Prototyping, Support, System Validation, Use Modes |

 

Success Prototyping with UltraScale VU440 devices

It’s been a while since Xilinx shipped the first UltraScale VU440 engineering sample devices to Synopsys so I thought it time to deliver a short update on development progress. It might be hard to see in the above but that is a picture of one of the new development HAPS systems for the UltraScale VU440 devices. I say hard to see not only as the picture quality is low but also because we have the system completely configured with intelligent interconnect as part of our stringent characterization and functional validation process.

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Posted in Admin and General, ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Project management, Real Time Prototyping, System Validation, UltraScale, Use Modes |

 

Fight Club: Automated vs. Hand Crafted Pin Multiplexing

This week a prototyping engineer challenged me that “his” customized and hand crafted pin multiplexing capability was “better” than the HAPS High Speed Time-Domain Multiplexing, HSTDM. My response, “Faster, maybe, better NO”. This blog explains why the HAPS HSTDM capability will beat out a custom coded multiplexing capability hands down every time.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, Project management, Support, Use Modes |

 

Deep Roots Aid Debug

I traveled from Oregon to California this week and visited the new Synopsys offices aka “The 690!” all I can say is wow, I want one. The Synopsys offices in Hillsboro Oregon are nice but we don’t have the new technology that the Synopsys CA offices got. Gym, cafeteria, bright nice cubes/office and Champagne on tap….. Of course one of these is a lie, can you guess which? Yes that’s right, no cube space can ever be nice. There is a HUGE hardware lab and I was able to wing it and get someone to flash me in, apparently I’m not on the authorized entry list “yet”. There are many HAPS stations for development and regression testing, one of the stations that caught my eye is pictured below

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Posted in ASIC Verification, Bug Hunting, Debug, Man Hours Savings |

 

Coming To A Lab Soon: Xilinx VU440 FPGA Devices

In late 2013 I blogged about the newly announced Xilinx UltraScale devices, the VU440 specifically that will be the largest FPGA device on the market: http://blogs.synopsys.com/breakingthethreelaws/2013/12/xilinx-fpga%E2%80%99s-for-fpga-based-prototyping/

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Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, Man Hours Savings, Milestones, Technical, Tips and Traps |

 

Recap of what you missed, impactful blogs from the last 3 months

During a customer meeting last week I found myself explaining many different topic’s all of which I have blogged about over the last couple of months. I suddenly realized that while I blog every week that many of you might not get time to read them every week and miss important information. Below is a list of what I think are the impactful blogs from the last couple of months, just in case you missed them.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, IP Validation, Man Hours Savings, Use Modes |

 

New Sexy Videos Posted

We have just uploaded a stack of product videos. Below is a list of the latest three. (I think they are sexy!!)

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Posted in ASIC Verification, Bug Hunting, Debug, DWC IP Prototyping Kits, Early Software Development, Humor, IP Validation, Man Hours Savings |

 

How to stand out in a sea of similarity

This week at SNUG Japan I presented on how you can utilize FPGA-based prototyping to differentiate your products. Basically the theme of the presentation was earliest, fastest and highest debug. The earlier a prototype is made available the more productive you can be with it translating into accelerated time to market. The faster the prototype the more tests or complex scenarios could be run translating into higher quality products. With earlier prototype availability and more complex software being run you need better debug capabilities to rapidly track down bugs. The presentation seemed to be very well received and if you have a SolvNet ID you should be able to find the presentation within the SNUG proceedings soon.

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Posted in Bug Hunting, DWC IP Prototyping Kits, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation |