Breaking The Three Laws

Archive for the 'ASIC Verification' Category

 

Intel’s FPGA-Based Prototyping presentations from SNUG Israel

Recently at  SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology guide so I highly recommend you review the material.

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Posted in ASIC Verification, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Project management, System Validation, Technical, Tips and Traps, Use Modes |

 

Expectation setting for FPGA-based prototyping

The myths of FPGA-based prototyping are still being proliferated and I have taken on a quest to educate the world on what FPGA-based prototyping really delivers. The latest myth propagation is seen below and was cut from a recent posting on a well-known industry website. You are all smart, you will be able to work out where it comes from. Fun read.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, Performance Optimization, System Validation, Use Modes |

 

Comparison of Prototyping bridge vs. Hybrid Prototypes

This week Synopsys’ announced the availability of the DesignWare Hybrid IP Prototyping Kits: http://www.synopsys.com/IP/ip-accelerated/Pages/hybrid-ip-prototyping-kits.aspx The Synopsys DesignWare® Hybrid IP Prototyping Kits pre-integrate a Virtualizer™ Development Kit (VDK) and a DesignWare IP Prototyping Kit to accelerate IP prototyping, software development and integration of DesignWare IP in 64-bit ARM®-based designs. Hybrid IP Prototyping Kits enable designers to accelerate hardware/software integration and full system validation, thus reducing the overall product design cycle. The included Linaro® Linux® software stack, reference drivers, and pre-verified DesignWare IP reference design allow users to start implementing and validating IP in an SoC context in minutes.

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Posted in ASIC Verification, Debug, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Use Modes |

 

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM…. Yes, we did this way back in 2010 with the launch of the HAPS-60 complete solution, and then raised the bar in 2012 with the launch of the evolutionary HAPS-70 complete solution. Synopsys HAPS is a proven integrated solution delivering the fastest time to operational prototype, highest system performance, superior debug and advanced capabilities including Hybrid Prototyping and global server farm access.

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Posted in Admin and General, ASIC Verification, Bug Hunting, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Real Time Prototyping, Support, System Validation, Use Modes |

 

Reduce WNS by up to 60%, sometime more

The WNS I am talking about is Worst Case Negative Slack and not White Nose Syndrome, a disease in North American bats which, as of 2012, was associated with at least 5.7 million to 6.7 million bat deaths. Please help and stop the spread of this nasty disease. Poor little bats have no defense against it. The WNS I’m going to talk about is Worst Case Negative Slack of a prototyping design, reduce WNS and prototype execution performance increases.

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Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Performance Optimization, Project management, System Validation, Use Modes |

 

Prototyping Over 700 Million ASIC Gates Using Xilinx Virtex-7 2000T FPGAs

You read the title correctly, this blog discusses prototyping over 700 Million ASIC gates using the Xilinx Virtex-7 2000T FPGA’s. To get to this capacity you need to utilize sixty four (64) FPGA’s. The picture above was taken in the Synopsys HAPS lab and shows part of our Super Chain testing. As noted previously, HAPS documented seamless deployable capacity is 288 Million ASIC gates, which is six HAPS-70 (four) FPGA systems chained together, a total of twenty four (24) FPGA’s. However we have customers where this is not enough. The HAPS solution is modular and scalable with base building blocks of x1, x2 and x4 FPGA systems and supported with a HAPS-Aware design tool flow.

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Posted in ASIC Verification, Debug, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, Man Hours Savings, Project management, Support |

 

Success Prototyping with UltraScale VU440 devices

It’s been a while since Xilinx shipped the first UltraScale VU440 engineering sample devices to Synopsys so I thought it time to deliver a short update on development progress. It might be hard to see in the above but that is a picture of one of the new development HAPS systems for the UltraScale VU440 devices. I say hard to see not only as the picture quality is low but also because we have the system completely configured with intelligent interconnect as part of our stringent characterization and functional validation process.

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Posted in Admin and General, ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Project management, Real Time Prototyping, System Validation, UltraScale, Use Modes |

 

Automated Timing Biased Partitioning

I spent a lot of time this week talking about timing biased automated partitioning which is the ability of the ProtoCompiler partition engine to generate a partition and pin multiplexing implementation with the goal of maximizing performance of the final prototype implementation. As it’s getting close to Easter I thought it was fitting to discuss ProtoCompiler’s Multi-Hop optimization algorithm. (Easter, Easter bunny, hop, you see what I did there?)

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Posted in ASIC Verification, FPGA-Based Prototyping, Tips and Traps |

 

Valuable Software Drive Validation

Software driven validation is becoming very popular as it enables the same SW code you are developing for the final product to be used to verify the product under development. This has multiple benefits such as reduced verification effort from minimizing duplicated effort to create test scenarios in addition to writing the actual SW code. It also flushes out more bugs as you are running the real SW code, or close to it, to verify the design under test so inherently it’s covering much of the user space. So why is not everyone verifying designs like this?

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Posted in ASIC Verification, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Real Time Prototyping, System Validation, Use Modes |

 

Fight Club: Automated vs. Hand Crafted Pin Multiplexing

This week a prototyping engineer challenged me that “his” customized and hand crafted pin multiplexing capability was “better” than the HAPS High Speed Time-Domain Multiplexing, HSTDM. My response, “Faster, maybe, better NO”. This blog explains why the HAPS HSTDM capability will beat out a custom coded multiplexing capability hands down every time.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, Project management, Support, Use Modes |