Breaking The Three Laws

Archive for the 'ASIC Verification' Category

 

Prototyping Low Power Functions Using UPF

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

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Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes

 

Part Deux: How many ASIC Gates does it take to fill an FPGA?

Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.

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Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes