Michael Posner

Michael (Mick) Posner joined Synopsys in 1994 and is currently director of product marketing responsible for integrated design solutions, including DesignWare® IP subsystems and IP hardening. Previously, Mick held various product marketing, application consultant, and technical marketing manager positions at Synopsys. He holds a bachelor’s degree in electronic and computer engineering from the University of Brighton, England. His expertise ranges from digital front-end to mixed-signal back-end design topics and FPGA-based prototyping.

Posts by Michael Posner:

Prototyping Low Power Functions Using UPF

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes

Understanding Xilinx System Logic Cells vs. Logic Cells

Recently I blogged on a change in the way Xilinx reports the capacity of their new UltraScale FPGA devices. At the end of the blog I left with the following questions

Posted in UltraScale

Performance, Performance, Performance, HAPS with ProtoCompiler Goes to 11

Ultimately when you hand-off your physical FPGA-based prototype to the end users there are only two things that they care about; Performance, Performance, Performance. I know I said there were only two things but performance is so important I listed it three times.

Posted in HAPS-80, Performance Optimization, UltraScale

Part Deux: How many ASIC Gates does it take to fill an FPGA?

Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.

Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes

How many ASIC Gates does it take to fill an FPGA?

Posted in Man Hours Savings, Milestones, Project management

You don’t buy a dog and bark yourself

I have a set of witty one liners which I use to respond to a variety of situations that I encounter in my everyday life. Some are insightful and designed to share my wisdom while others are just supposed to be a little humorous. The title of this blog is one and I have listed a set of my favorite quotes below including the typical situations which I use them. Feel free to use these in your everyday situations as I am sure they will be as impactful for you as they are for me. I might not have been the first person to come up with these quotes so don’t get upset if you use the same ones already.

Posted in Humor

HT 3 Connector Utilization Recommendation

I snapped off the picture of the HAPS-70 system below at a recent customer meeting and it gave me the idea for this blog. Other than the fact that the systems look “well sexy” (Yes, usually a term you do not hear used to describe hardware) this picture also highlights the flexible nature of the system interconnect architecture with the high performance coax cables and recommended usage.

Posted in FPGA-Based Prototyping, Getting Started, Tips and Traps