Posted by Michael Posner on April 1, 2016
While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:
This is the demo setup for the DesignWare IP for PCIe Gen4 which is the latest and fast 16 Gb/s PCIe transfer solution. (Sorry for the low quality mobile phone pic). This is the platform which we have been using around the world to demonstrate our hardware validated PCIe Gen4 solution.
At the top of the pic is the ARC platform which is used to execute software to manage the DesignWare PCIe controller core which is modeled in the HAPS-DX system in the center of the pic. The large daughter board at the bottom houses the testchip of the mixed signal PHY. It connects to a simple PCIe backplane which is the card right at the bottom under the PHY daughter board, almost out of sight. The backplane connects up to an almost identical setup on the backside. One side is the root complex, other is the device, both using DesignWare IP as at this time their is practically no PCIe Gen4 hosts on the market.
This reminded me of a key value of FPGA-based prototyping…. EARLY…. This HAPS-based prototyping setup enables validation of hardware and software for a cutting edge protocol. Below you can see a video of the DesignWare PCIe Gen4 setup in action
Can’t embed the video so please click this: https://www.youtube.com/watch?v=P2G2nGqgf2E
You can also find out more about the DesignWare PCIe Gen4 solution on the Express yourself blog, https://blogs.synopsys.com/expressyourself/2015/11/13/the-worlds-second-pcie-gen4-system-arm-beats-intel/ and here: https://blogs.synopsys.com/expressyourself/2016/03/04/the-long-lost-video-the-worlds-2nd-pcie-gen4-system/ and Synopsys webpages here.
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