Breaking The Three Laws


Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

A recent web seminar presented the various debug scenarios and maps which debug capabilities to use for the particular scenario.

HAPS Debug Visibility Web Seminar

I highly recommend you take the time and watch the seminar as it covers not only the traditional physical prototype debug capability but also introduces the new capabilities such as HAPS Deep Trace Debug, the ability to capture huge amounts of debug data as well as HAPS Global State Visibility. Global State Visibility has always been seen as the Holy Grail of FPGA-based prototyping, the ability to trace the state of all design registers, dynamically, without the need to pre-define of instrument.

HAPS & ProtoCompiler Debug Visibility Solutions

The web seminar also includes a mention of utilizing the other capabilities such as HAPS Real Time Debug enabling a debug connection to a Logic Analyzer and cross triggering to aid in HW/SW debug.

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