Posted by Michael Posner on January 8, 2016
Happy New Year and all that. What an fantastic 2015 for physical prototyping and I expect 2016 to be even better now the Xilinx UltraScale based solutions are rolling out. Of course the highlight of the work year for me was the launch of the HAPS-80 with ProtoCompiler.
HAPS-80 with ProtoCompiler Key Benefits
Below is a flashback to 2015’s Top 10 blog topics as rated by readership hits. #1, most popular.
#1 : https://blogs.synopsys.com/breakingthethreelaws/2015/02/how-many-asic-gates-does-it-take-to-fill-an-fpga/ No one seemed to get the relevance of the chicken crossing the road but that’s just how my brain works. The blog title was like a joke, “why did the chicken cross the road?”, “How many ASIC gates does it take to fill and FPGA?” do you see the connection?
#2 : https://blogs.synopsys.com/breakingthethreelaws/2015/02/part-deux-how-many-asic-gates-does-it-take-to-fill-an-fpga/ Second part of the blog post which explains how to calculate how many ASIC gates it takes to fill and FPGA. Spoiler alert… there is no golden calculation which can be used for this purpose.
#3 : https://blogs.synopsys.com/breakingthethreelaws/2015/09/introducing-haps-80-with-fully-integrated-protocompiler-shifting-the-market-to-an-integrated-prototyping-solution/ Introduction of the key benefits of HAPS-80 and ProtoCompiler
#4 : https://blogs.synopsys.com/breakingthethreelaws/2015/12/understanding-xilinx-system-logic-cells-vs-logic-cells/ The answer to why Xilinx changes the way they report FPGA capacity and the technical details behind it
#5 : https://blogs.synopsys.com/breakingthethreelaws/2015/10/xilinx-ultrascale-vu440-device-now-25-greater-capacity/ Xilinx has changed the way they report FPGA capacity, learn more about it here
#6 : https://blogs.synopsys.com/breakingthethreelaws/2015/08/performance-boost-from-xilinx-ultrascale-based-prototypes/ What to expect in respect to performance when moving to Xilinx UltraScale based prototype.
#7 : https://blogs.synopsys.com/breakingthethreelaws/2015/06/highest-performance-xilinx-ultrascale-based-prototypes/ Discusses what it takes to get the highest performance out of your Xilinx UltraScale based prototype. You need a combination of hardware, features, IP and a tool flow which considers timing all the way through the flow.
#8 : https://blogs.synopsys.com/breakingthethreelaws/2015/07/xilinx-ultrascale-vu440-based-haps-solution-shipping-hapsprotocompiler/ Covers the key benefits of the HAPS-80 with ProtoCompiler and links to blogs detailing each key feature.
#9 : https://blogs.synopsys.com/breakingthethreelaws/2015/03/automated-timing-biased-partitioning/ Discusses how to eliminate or reduce the number of multi-hop paths in a multi-FPGA partitioned design. Multi-Hop paths negatively impact overall system performance.
#10 : https://blogs.synopsys.com/breakingthethreelaws/2015/08/how-to-run-your-multi-fpga-prototype-at-ludicrous-speed/ What it takes to run your multi-FPGA prototype at the very highest of performance, no pin multiplexing.
#11 : https://blogs.synopsys.com/breakingthethreelaws/2015/05/comparison-of-prototyping-bridge-vs-hybrid-prototypes/ Discussing the differences & benefits of what the market calls a prototyping bridge (interface from host to prototype hardware) vs. Hybrid Prototyping
(Yes, I know the list goes to 11……..)
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I did not relax over the Christmas/New Year break, check out my fitbit’s report of just one of my days.
Note the number of floors climbed. That’s not an error, that’s how many you get when you hike up the side of a mountain for 3 1/2 hours.
I also went from beard back to stubble. The beard did help with the cold weather face protection.