Breaking The Three Laws


Results from Xilinx UltraScale VU440 based HAPS-80 with HAPS ProtoCompiler

I visited the Synopsys offices again this week and sat down with a couple of the R&D engineers to discuss what our customers should expect in respect to performance when they utilize the new HAPS-80 and HAPS ProtoCompiler. I blogged about this a while back, I now have the latest information.

HAPS-80 with HAPS ProtoCompiler production systems in the lab

These results here are for a multi-FPGA design using the HAPS ProtoCompiler 2016.03 code base targeting the new HAPS-80 system. In this case we are comparing against a design running on HAPS-70 using HAPS ProtoCompiler. The focus of the test is to measure the performance of the pin multiplexing capability which is the typical bottleneck of system performance within a multi-FPGA physical prototype. The results are fantastic, HAPS-80 with HAPS ProtoCompiler 2016.03 multi-FPGA pin multiplexing capability using Synopsys’ proprietary HSTDM is exhibiting an increase in performance on average of 15% right out of the box. This is a direct apples to apples comparison for the same pin multiplexing ratio. It’s of course possible that with the move to the new systems that other factors also improve the achievable performance. The R&D team also believe there is room for improvement but would like more time to stress test the higher performance version to ensure 100% reliable operation across all HAPS-80 systems.

There have also been enhancements made in HAPS ProtoCompiler 2016.03 timing driven system route engine that on average cuts ~8ns off the critical path. Take for example your systems are currently running at 15 MHz which is a 66ns period. Shave off 8ns resulting in a period of 58ns and you increase the system performance to over 17 MHz a 14% increase. Combine this with the faster HAPS-80 with HAPS ProtoCompiler HSTDM capability and there is a potential for significant performance improvements. This capability is available for both HAPS-70 and HAPS-80.

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