Breaking The Three Laws

Archive for 2016

 

Hitting the Mark

Just in case you had not noticed, the prototyping blog can now be found here: https://blogs.synopsys.com/hittingthemark/

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Posted in Admin and General | Comments Off on Hitting the Mark

 

Read Issue #1 Prototyping Newsletter: Reduce Risk and Speed Time-to-Market with End-to-End Prototyping

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Posted in Prototyping newsletter | Comments Off on Read Issue #1 Prototyping Newsletter: Reduce Risk and Speed Time-to-Market with End-to-End Prototyping

 

Which is your favorite FPGA-based prototyping setup?

Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards,

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Posted in Admin and General, HAPS-80, Support, UltraScale | Comments Off on Which is your favorite FPGA-based prototyping setup?

 

Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)

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Posted in ASIC Verification, Bug Hunting, Debug, FPGA-Based Prototyping, HAPS-70, HAPS-80, Man Hours Savings, Performance Optimization, Real Time Prototyping, Tips and Traps, UltraScale | Comments Off on Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

 

Verifying Power Management Modes, both Software and Hardware

Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!”

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation, UltraScale, UPF, Use Modes | Comments Off on Verifying Power Management Modes, both Software and Hardware

 

ESD Precautions Essential for prototype handling

Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape.

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Posted in Admin and General, HAPS-80, UltraScale | Comments Off on ESD Precautions Essential for prototype handling

 

Prototyping enables worlds first PCIe Gen4 (16 Gb/s) demonstration

While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:

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Posted in DWC IP Prototyping Kits, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | Comments Off on Prototyping enables worlds first PCIe Gen4 (16 Gb/s) demonstration

 

It’s not too late to attend SNUG Silicon valley

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes | Comments Off on It’s not too late to attend SNUG Silicon valley

 

What’s in it for me? The market shift to integrated Physical Prototyping

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off on What’s in it for me? The market shift to integrated Physical Prototyping

 

Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale | Comments Off on Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities