Breaking The Three Laws

Archive for 2015

 

How to achieve a simulator like debugging experience with FPGA-based prototyping

This week we will discuss the simulator like debugging experience that users of the new HAPS-80 with ProtoCompiler solution get. The new solution includes built-in debug which means that the ProtoCompiler flow incorporates debug and the HAPS-80 hardware has debug capabilities physically built in. The ProtoCompiler flow ensures that the inclusion of debug it mostly seamless to the user and the HAPS-80 built in debug hardware ensures that the advanced capabilities are available without the need to purchase additional hardware.

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Posted in Bug Hunting, Debug, HAPS-80, UltraScale | Comments Off on How to achieve a simulator like debugging experience with FPGA-based prototyping

 

Overcoming the three phases of prototype bring-up

Over the next couple of weeks I’ll blog with more details on the key capabilities of the newly available HAPS-80 with ProtoCompiler integrated solution.

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, Man Hours Savings, Performance Optimization, UltraScale | Comments Off on Overcoming the three phases of prototype bring-up

 

Introducing HAPS-80 with Fully Integrated ProtoCompiler – Shifting the Market to an Integrated Prototyping Solution

Drum roll please…… Introducing the latest generation FPGA-based prototype, the HAPS-80 with ProtoCompiler solution is now available. Above I’m pictured introducing the new fully integrated solution to a packed room at SNUG in Taiwan. Below I’m staged in front of the physical side of the new solution, the HAPS-80 hardware itself. The unit on the right, the unit on the left sort of behind me is the previous generation the HAPS-70.

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Posted in HAPS-80, UltraScale | Comments Off on Introducing HAPS-80 with Fully Integrated ProtoCompiler – Shifting the Market to an Integrated Prototyping Solution

 

Preventing Electrostatic Discharge

Recently I witnessed a user of our HAPS-70 systems touch the system without taking any Electrostatic Discharge, ESD, precautions. While the units are prototypes and it’s expected that they are customized with both off the shelf and custom daughter boards and of course design specific FPGA bit files, you cannot forget ESD precautions. The HAPS-70 systems utilize the Xilinx Virtex-7 2000T FPGA’s which are fabricated in a 28nm process. The smaller the geometry the more susceptible they are to ESD. You must never, never, never handle FPGA-based prototyping hardware without taking ESD precautions.

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Posted in Admin and General | Comments Off on Preventing Electrostatic Discharge

 

Customer experiences with ProtoCompiler for HAPS

Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.

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Posted in ASIC Verification, Early Software Development, In-System Software Validation, Man Hours Savings, Performance Optimization, Project management | Comments Off on Customer experiences with ProtoCompiler for HAPS

 

Would you like 2X Performance AND Reduced Tool Runtime (Turn-around-Time)?

Above is a picture of HAPS High Speed Time Domain Multiplexing (HAPS HSTSM) being tested across the current HAPS-70 and the new HAPS systems based on Xilinx UltraScale FPGA devices.

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Posted in Bug Hunting, Man Hours Savings, Performance Optimization, Project management, UltraScale | Comments Off on Would you like 2X Performance AND Reduced Tool Runtime (Turn-around-Time)?

 

Double performance with SLR to IO Bank to Connector 1 to 1 mapping for Xilinx UltraScale VU440

A long time ago in a blog since forgotten I talked about the importance of 1:1 mapping between the Xilinx FPGA Super Logic Region, SLR, to IO Bank to Connector. The result of which can be as much as 2X system performance thanks to efficient mapping of the design to the FPGA.

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Posted in IP Validation, UltraScale | Comments Off on Double performance with SLR to IO Bank to Connector 1 to 1 mapping for Xilinx UltraScale VU440

 

Performance boost from Xilinx UltraScale based prototypes

Everybody wants to know how much faster their FPGA-based prototype will run when they migrate to a Xilinx UltraScale VU440 based setup. This blog sets about trying to answer that very question. Sadly there is not a simple equation that can be applied as final system performance is highly design specific. Increase in performance falls into three or so buckets

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Posted in UltraScale | Comments Off on Performance boost from Xilinx UltraScale based prototypes

 

Prototype ready IP for immediate productivity

Back in 2011 I had a vision, a vision for how users of both IP and FPGA-Based Prototypes could be more productive. The problems these users faced was not to do with bugs or lack of capabilities in the products but from the fact that the usage crossed between the two products. IP users traditionally are not experienced prototypers and prototypers lacked IP specific knowledge. Of course this was not helped by the fact that the IP did not document it’s prototyping specific needs. For example, the IP is optimized for ASIC deployment and when you prototype it the clocking, reset and rams sometimes need to be modified to fit into a FPGA environment. Another issue is that as it’s ASIC IP not all configurations can be physically supported in FPGA. For example while the IP might support up to 16 IO ports on the prototype you might only be physically implement up to 4.

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Posted in DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | Comments Off on Prototype ready IP for immediate productivity

 

How To Run Your Multi-FPGA Prototype at Ludicrous Speed

In this blog I’m going to explain how you can run a multi-FPGA HAPS prototype at up to 100 MHz !!!!!

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Posted in Performance Optimization, UltraScale | Comments Off on How To Run Your Multi-FPGA Prototype at Ludicrous Speed