Posted by Michael Posner on December 6, 2015
Recently I blogged on a change in the way Xilinx reports the capacity of their new UltraScale FPGA devices. At the end of the blog I left with the following questions
Inquisitive minds are asking the following questions:-
In reverse, Xilinx does not have a time machine (sad L) and has not auto-magically built more capacity into the Xilinx UltraScale FPGA devices since they launched them. What they have done is changed their technology which requires an update to how they count the capacity of their FPGA’s.
First the challenge
These slides pretty much speak for themselves so no need for me to repeat.
Now introducing System Logic Cells
Key point here IMO is that this change is more consistent with how other vendors report their capacity so in essence there is a move towards a more standardized approach. It should be noted that each vendor still counts differently than each other but that’s because their technologies are different.
Now what is a System Logic Cell? First lets review the Virtex-7 architecture.
The picture above, click to enlarge, is of the Xilinx 7 Series CLB, consisting of two slices per CLB.
Now lets compare and contrast the older Xilinx 7 series CLB with the Xilinx UltraScale architecture.
<caution, technical content>
If we now look at the Xilinx UltraScale™ architecture CLB, a CLB and a slice are now one in the same. Xilinx have built new dedicated inputs for each flip-flop so that they no longer need to route through a look-up table to get access to the second flip-flop. This should reduce the overall LUT utilization. By eliminating the concept of the slice, this enables Xilinx to add a new wide function MUX at the output of the look-up tables. Now Xilinx can build functions that are made up of 8 LUTs and can all be cascaded together to build wider functions. This also allows Xilinx to build twice as wide distributed RAMs vs. previously. To support that Xilinx added a wider carry chain.
In addition, Xilinx doubled the number of clock enables. One of the most significant factors when it comes to getting higher CLB packing is having additional clock enables so that the tools can combine functions together in the same CLB that may have different clock-enable inputs on them. Finally, Xilinx also put clock-enable ignore, reset ignore and local reset inversion on all flip-flops. All this allows for tighter packing. In UltraScale, Xilinx can now pack flip-flops together where some of them may be using a clock-enable, some may not be. Same thing on the reset side. Some flip-flops can use a reset, otherwise if they don’t have a resent that’s okay. They can still be packed into the same CLB and Xilinx will invert the polarity of the reset locally rather than needing to route through a LUT just to simply change the polarity of the reset.
So all in all Xilinx’s data seems to back up the new capacity calculation. Of course the proof is in the pudding and especially in physical prototyping the only realistic way to gauge your capacity need is to run it through a tool flow such as Synopsys’ ProtoCompiler. This way you will have a more accurate design specific capacity representation. Of course this blog would have been far simpler if Xilinx has built a time machine…
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