Breaking The Three Laws


Preventing Electrostatic Discharge

Lab sign posted in Synopsys. Notice the additional sign banning marketing from the hardware lab

Recently I witnessed a user of our HAPS-70 systems touch the system without taking any Electrostatic Discharge, ESD, precautions. While the units are prototypes and it’s expected that they are customized with both off the shelf and custom daughter boards and of course design specific FPGA bit files, you cannot forget ESD precautions. The HAPS-70 systems utilize the Xilinx Virtex-7 2000T FPGA’s which are fabricated in a 28nm process. The smaller the geometry the more susceptible they are to ESD. You must never, never, never handle FPGA-based prototyping hardware without taking ESD precautions.

The following table illustrates the typical magnitude of the voltage developed in some common situations

ESD build up

Here are Ten points for helping eliminate ESD damage to prototyping hardware

  1. Make sure you have a reliable ground point available near the work site
  2. Connect your body to the ground point with a wrist strap.
  3. Ground all equipment you are working on with ground straps
  4. Handle components only on a grounded anti-static work surface.
  5. Do not wear clothing which generates static electric charges every time you move.
  6. Do not handle static generating objects while working on hardware.
  7. Store all chips and other components in appropriate anti-static containers.
  8. Keep all daughter cards in anti-static envelopes until required.
  9. Be sure to turn off the power and remove the power plug from all equipment before working on it.
  10. Do not plug in or remove devices/daughter boards while the power is on.

This is not a complete list but covers the basic handling recommendations to reduce ESD damage.

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I attended a Synopsys event this week and as a little fun we were able to get a caricature done.

Mick is Evil?

I think they captured me very well.

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