Posted by Michael Posner on September 25, 2015
Over the next couple of weeks I’ll blog with more details on the key capabilities of the newly available HAPS-80 with ProtoCompiler integrated solution.
Today’s focus is on the design flow and time to first prototype operation being reduced to on average less than two weeks. Based on the FPGA-based Prototype Methodology Manual survey results this is still seen as the number #1 challenge to prototypers.
Addressing time to first prototype means addressing the three phases of prototyping, making the design FPGA friendly, bring-up and debug and finally performance optimization. The first phase, make the design FPGA friendly, is all about automation. One of the three laws of prototyping is that ASIC code is FPGA hostile, there is no way around that so the more that can be done to automate the process the more seamless the flow becomes.
This is exactly what ProtoCompiler for HAPS delivers, automation throughout the flow to hardware. Automation including gated clocks conversion, clock replication, memory translation, partitioning and pin multiplexing insertion all the way through to guided place and route. The complete flow can be scripted for repeatability. This is the key capability in reducing the time to first prototype to on average less than two weeks. At this point you have FPGA bit files ready to test on the HAPS systems
The second phase if the bring-up and debug of the platform.
In a perfect world the prototype would function out of the box, which is the case some of the time, but unfortunately not all of the time. In this phase the prototype engineer wants to check the system is configured correctly and rapidly debug. HAPS-80 with ProtoCompiler enables both. The HAPS built-in system check capability ensures that interconnect and daughter boards are correctly installed, match the design description and meet the required performance. Debug can be rapidly inserted not requiring a re-compile speeding up the design bring-up debug process. We highly recommend an incremental bring-up strategy of individual blocks then subsystem and finally SoC. ProtoCompiler supports an IP to SoC flow enabling this bring up strategy as lower level blocks can be integrated into the larger context of the design with reuse of the constraints developed at the block level.
At this point the HAPS-based prototype can be handed off to the target teams for continued bring up testing and early software development. The 3rd phase, performance optimization is also typically a fast iteration but the more focus this stage is given the better the results can be.
ProtoCompiler is designed to get to a result as fast as possible with out of the box high performance. If you have a little extra time to spare this performance can be optimized. In ProtoCompiler this is simply a change of configuration from TTFP (Time to First Prototype) mode to performance optimized mode. In the optimization and tuning mode the compilation optimization is enabled, synthesis target is highest performance, different partition goals and so on. While the turn-around time from RTL to bit file is increased the typical result is the highest performance.
So as you can see, HAPS-80 with ProtoCompiler successfully addresses the time to first prototype achieving on average less than two weeks to operation. Next week, built-in debug
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Last week I spent the weekend in Shanghai. To pass some of the time I visited the Shanghai Science and Technology Museum I really enjoyed it.
What an amazing looking museum.
While I visited all exhibit halls I enjoyed the world of robots the most
This hall had some great exhibits with dancing robots, archery against a robot and much more. I really liked the little robot pictured below who put on a hip hop dance show and then more classic Chinese dancing.
There was even a robot who would solve a rubix cube. You mess it up, it solved it in typically less than 1 minute.