Posted by Michael Posner on August 29, 2015
Above is a picture of HAPS High Speed Time Domain Multiplexing (HAPS HSTSM) being tested across the current HAPS-70 and the new HAPS systems based on Xilinx UltraScale FPGA devices.
This week I’ve been busy presenting our next generation HAPS Solution, based on Xilinx UltraScale VU440 FPGA’s, to a number of key customers. First of all they love it, the benefit of the co-designed solution combining HAPS and ProtoCompiler are easily recognized. In many cases it’s highly possible that the new solution could increase performance by as much as 2X with a tool flow with reduced runtime. I’m personally confident that the new generation solution will be the most successful HAPS product to date. Each generation of HAPS has been more successful, dollar wise and sales unit volume wise, than the generation before it.
The customers I’ve been presenting to are all existing HAPS-70 users so one of the focus points was to ensure they understood that the HAPS-70 and this new generation are interoperable with each other. Not only does the hardware seamlessly chain, one cable between systems is all that is needed for the system to look like a single setup, but the design tool of choice, ProtoCompiler, supports mixing both Xilinx Virtex-7 and Xilinx UltraScale systems in one project. Of course when you mix systems don’t expect the older system to support the new capabilities. In a mixed setup the feature set supported between the two is dictated by the older generation.
I’ve seen many users get caught when they develop their own capabilities on one of their in-house developed FPGA boards. They tune the capability to the piece of hardware they are running only to find out that it does not run on any of the other FPGA boards they have. This is not an issue with HAPS and ProtoCompiler as they are co-designed and co-tested.
Co-design is the term we use for the parallel development of capabilities which require both hardware and tool support. The HAPS High Speed Time-Domain multiplexing and HAPS Deep Trace Debug are great examples of co-designed capabilities. The hardware has to be designed to support the capability and the ProtoCompiler tool has to include the feature to insert and deploy it. The advantage of co-designed capabilities is that the HAPS hardware characterization data is built into the ProtoCompiler tool ensuring that the feature is correct constrained. A version of this constrained feature is then used as part of the production test for the HAPS hardware ensuring that when the capability is used it always runs in a reliable and highest performance fashion. We continuously test the production implementation against the production HAPS systems ensuring backward compatibility in addition to reliable operation you can trust. If your prototype is acting funny you can be assured that it’s a legitimate issue in YOUR RTL or YOUR software and not an artifact of the HAPS capabilities.
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I’m presenting at SNUG Taiwan in a couple of weeks. If you happen to be around the SNUG location, drop in and say hello to me. I’ll be presenting the new HAPS systems and will have a live demo running on the new Xilinx UltraScale based system as well.